公开(公告)号：US07061058B2

公开(公告)日：2006-06-13

申请号：US11148805

申请日：2005-06-09

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Robert C. Bowen ,  Haowen Bu

IPC分类号： H01L29/10

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/91

摘要： A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

摘要翻译： 提供了在晶体管中形成逆行阱的方法。 形成在基板和栅极之间具有基板，栅极和栅极氧化物层的晶体管结构。 衬底包括通常位于栅极下方的沟道区域。 将第一掺杂剂注入沟道区。 将第二掺杂剂注入到衬底中以形成掺杂源极区和掺杂漏极区。 将第三掺杂剂注入到栅极氧化物层中。 进行源极/漏极退火以分别在掺杂源极区域和掺杂漏极区域中形成源极和漏极。 源极/漏极退火使得沟道区域中的第一掺杂剂的一部分被第三掺杂剂吸引到栅极氧化物层中。

公开(公告)号：US07060579B2

公开(公告)日：2006-06-13

申请号：US10902360

申请日：2004-07-29

申请人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

发明人： PR Chidambaram ,  Lindsey Hall ,  Haowen Bu

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

摘要： A method (100) of forming a transistor includes forming a gate structure (108) over a semiconductor body and forming recesses (112) using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon (114) comprising stress-inducing species in the recesses. The source and drain regions are then implanted (120) in the semiconductor body on opposing sides of the gate structure.

公开(公告)号：US20060068541A1

公开(公告)日：2006-03-30

申请号：US10950138

申请日：2004-09-24

申请人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

发明人： PR Chidambaram ,  Srinivasan Chakravarthi ,  Haowen Bu ,  Rajesh Khamankar

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

摘要： A method (200) fabricating a semiconductor device is disclosed. A poly oxide layer is formed over gate electrodes (210) on a semiconductor body and active regions defined within the semiconductor body in PMOS and NMOS regions. A nitride containing cap oxide layer is formed over the grown poly oxide layer (212). Offset spacers are formed adjacent to sidewalls of the gate electrodes (216). Extension regions are then formed (214) within the PMOS region and the NMOS region. Sidewall spacers are formed (218) adjacent to the sidewalls of the gate. electrodes. An n-type dopant is implanted into the NMOS region to form source/drain regions and a p-type dopant is implanted with an overdose amount into the PMOS region to form the source/drain regions within the PMOS region (220). A poly cap layer is formed over the device (222) and an anneal or other thermal process is performed (224) that causes the p-type dopant to diffuse into the nitride containing cap oxide layer and obtain a selected dopant profile having sufficient lateral abruptness.

摘要翻译： 公开了制造半导体器件的方法（200）。 在半导体主体上的栅电极（210）上形成多个氧化物层，以及在PMOS和NMOS区域内限定在半导体本体内的有源区。 在生长的多晶氧化物层（212）上形成含氮化物的氧化物层。 邻近栅电极（216）的侧壁形成偏移间隔物。 然后在PMOS区域和NMOS区域内形成延伸区域（214）。 侧壁间隔件形成（218）邻近门的侧壁。 电极。 将n型掺杂剂注入到NMOS区域中以形成源极/漏极区域，并且将过量剂量的p型掺杂剂注入到PMOS区域中以在PMOS区域（220）内形成源极/漏极区域。 在器件（222）之上形成多晶硅层，并执行退火或其它热处理（224），使得p型掺杂剂扩散到含氮化物的氧化物层中，并获得具有足够横向突变性的选定掺杂剂分布 。

公开(公告)号：US07012028B2

公开(公告)日：2006-03-14

申请号：US10899359

申请日：2004-07-26

申请人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar

发明人： Haowen Bu ,  PR Chidambaram ,  Rajesh Khamankar

IPC分类号： H01I21/302 ,  H01I21/461

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74).

摘要翻译： 提出了晶体管制造方法（50），其中沿着晶体管栅极（114）的侧面形成可收缩的侧壁间隔物（120），并且在形成侧壁间隔物（74）之后执行源极/漏极注入（74） 120）。 然后通过在源极/漏极注入（74）之后退火可收缩侧壁间隔物材料（76）来减小侧壁间隔物宽度。

公开(公告)号：US06921703B2

公开(公告)日：2005-07-26

申请号：US10436848

申请日：2003-05-13

申请人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28202 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US09177806B2

公开(公告)日：2015-11-03

申请号：US13017828

申请日：2011-01-31

申请人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC分类号： H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC分类号： H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

摘要翻译： 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US08546259B2

公开(公告)日：2013-10-01

申请号：US11861421

申请日：2007-09-26

申请人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

发明人： Juanita DeLoach ,  Jiong-Ping Lu ,  Haowen Bu

IPC分类号： H01L21/44

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/7833

摘要： Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.

摘要翻译： 通常制造半导体部件，其包括硅化镍层，例如，作为晶体管部件中的栅电极的一部分，其可以通过在半导体衬底的含硅区域上形成镍层，然后进行热退火 半导体衬底以产生硅化镍。 然而，镍可能在热退火期间扩散到硅中，并且可能形成不期望地增加晶体管中的薄层电阻的晶体。 碳可以与镍一起放置以用作扩散抑制剂和/或防止在热退火期间形成镍晶体。 公开了利用该技术的方法以及根据该技术形成的半导体部件。

公开(公告)号：US20130056811A1

公开(公告)日：2013-03-07

申请号：US13432736

申请日：2012-03-28

申请人： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

发明人： Bo-Yang Lin ,  Yen Lee ,  Haowen Bu ,  Mark Robert Visokay

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L29/92

CPC分类号： H01L21/02225 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/57

摘要： An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

摘要翻译： 通过等离子体增强化学气相沉积（PECVD）沉积氮化硅的无氨方法。 将硅烷（SiH4）和氮（N2）的源气体提供给平行板等离子体反应器，其中能量电容耦合到等离子体，并且其中待处理的晶片已经被放置在支撑电极处。 将低频RF能量（例如，360kHz）施加到支撑电极; 可选地，将高频RF能量（例如，13.56MHz）提供给并联电极。 工艺温度高于350℃，压力约为2.5托。 存在于所得氮化硅膜中的任何氢由N-H键而不是Si-H键结合，因此与膜更牢固地结合。 氮化硅可用作铁电材料的钝化剂，如果被氢气污染，则可能会电解。

公开(公告)号：US07939400B2

公开(公告)日：2011-05-10

申请号：US12235766

申请日：2008-09-23

申请人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

发明人： Ting Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

IPC分类号： H01L21/8238

CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

公开(公告)号：US07670892B2

公开(公告)日：2010-03-02

申请号：US11268040

申请日：2005-11-07

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。