公开(公告)号：US06184150B2

公开(公告)日：2001-02-06

申请号：US08960104

申请日：1997-10-27

申请人： Chan-Lon Yang ,  Mei Chang ,  Paul Arleo ,  Haojiang Li ,  Hyman Levinstein

发明人： Chan-Lon Yang ,  Mei Chang ,  Paul Arleo ,  Haojiang Li ,  Hyman Levinstein

IPC分类号： H01L21302

CPC分类号： H01J37/32871 ,  H01J37/321 ,  H01J2237/3346 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/3185

摘要： A plasma etch process is described for the etching of oxide with a high selectivity to nitride, including nitride formed on uneven surfaces of a substrate, e.g., on sidewalls of steps on an integrated circuit structure. The addition of a hydrogen-bearing gas to C4F8 or C2F6 etch gases and a scavenger for fluorine, in a plasma etch process for etching oxide in preference to nitride, results in a high selectivity to nitride which is preserved regardless of the topography of the nitride portions of the substrate surface.

摘要翻译： 描述了用于蚀刻具有对氮化物的高选择性的氧化物的等离子体蚀刻工艺，包括在衬底的不平坦表面上形成的氮化物，例如在集成电路结构上的台阶侧壁上。 在氮化物优先蚀刻氧化物的等离子体蚀刻工艺中，向C4F8或C2F6蚀刻气体和氟清除剂中添加含氢气体导致氮化物的高选择性，而与氮化物的形貌无关 基板表面的部分。

公开(公告)号：US6083845A

公开(公告)日：2000-07-04

申请号：US255678

申请日：1999-02-23

申请人： Chan-Lon Yang ,  Tong-Yu Chen

发明人： Chan-Lon Yang ,  Tong-Yu Chen

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76816

摘要： An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.

摘要翻译： 在高密度等离子体蚀刻系统中使用蚀刻方法来蚀刻氧化硅介电层以形成不同深度的开口。 该方法使用C4H8，CH2F2和Ar的混合物作为蚀刻气体源来蚀刻氧化硅介电层，形成第一深度的多个开口。 使用C4H8，CO和Ar的混合物作为蚀刻气体源来蚀刻由第一开口暴露的氧化硅介电层，使得开口加深到第二深度。 使用C4H8，CH2F2，CO和Ar的混合物作为蚀刻气体源，蚀刻由开口暴露的氧化硅介电层，使得开口加深到第三深度和第四深度。

公开(公告)号：US5990017A

公开(公告)日：1999-11-23

申请号：US104550

申请日：1998-06-25

申请人： Kenneth Collins ,  Michael Rice ,  David Groechel ,  Gerald Yin ,  Jon Mohn ,  Craig Roderick ,  Douglas Buchberger ,  Chan-Lon Yang ,  Jerry Wong ,  Jeffrey Marks ,  Peter Keswick

发明人： Kenneth Collins ,  Michael Rice ,  David Groechel ,  Gerald Yin ,  Jon Mohn ,  Craig Roderick ,  Douglas Buchberger ,  Chan-Lon Yang ,  Jerry Wong ,  Jeffrey Marks ,  Peter Keswick

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01J37/321 ,  H01J37/32082 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/32458 ,  H01J37/32467 ,  H01J37/32522 ,  H01J37/32688 ,  H01J37/32706 ,  H01J37/32871 ,  H01L21/31116 ,  H01F2029/143 ,  H01J2237/3343 ,  H01J2237/3345 ,  H01J2237/3346 ,  H01J2237/3382

摘要： A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.

公开(公告)号：US5312778A

公开(公告)日：1994-05-17

申请号：US618142

申请日：1990-11-23

申请人： Kenneth S. Collins ,  Chan-Lon Yang ,  John M. White

发明人： Kenneth S. Collins ,  Chan-Lon Yang ,  John M. White

IPC分类号： C23C14/35 ,  C23C14/40 ,  C23C16/50 ,  C23C16/509 ,  C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H05H1/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/463

CPC分类号： H01J37/32082 ,  C23C16/509 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32623 ,  H05H1/46

摘要： A method for plasma processing characterized by the steps of disposing a wafer proximate to a cathode within a process chamber, releasing a gas into the chamber, applying R.F. power in the VHF/UHF frequency range to the cathode to form a plasma within the chamber, developing a magnetic field within the chamber having flux lines substantially perpendicular to the surface of the wafer, and varying the strength of the magnetic field until a desired cathode sheath voltage is attained. The apparatus includes a chamber, a wafer-supporting cathode disposed within the chamber, a mechanism for introducing gas into the chamber, an R.F. power source coupled to the cathode operating in the frequency from about 50-800 megahertz, an electromagnetic coil disposed around the chamber adapted to develop a magnetic field within the chamber which is substantially perpendicular to the wafer and a variable output power supply coupled to the coil to vary the magnetic field strength and therefore the cathode sheath voltage within the chamber.

摘要翻译： 一种用于等离子体处理的方法，其特征在于以下步骤：在处理室内设置靠近阴极的晶片，将气体释放到室中，施加R.F. 在VHF / UHF频率范围内的功率到阴极以在室内形成等离子体，在室内形成具有基本上垂直于晶片表面的磁通线的磁场，并且改变磁场的强度，直到所需的阴极 获得鞘电压。 该装置包括腔室，设置在腔室内的晶片支撑阴极，用于将气体引入腔室的机构，R.F. 电源，其耦合到以大约50-800兆赫的频率工作的阴极;设置在所述腔室周围的电磁线圈，其适于在所述腔室内开发基本上垂直于所述晶片的磁场;以及耦合到所述线圈的可变输出电源 以改变室内的磁场强度和因此的阴极护套电压。

公开(公告)号：US5300460A

公开(公告)日：1994-04-05

申请号：US32744

申请日：1993-03-16

申请人： Kenneth S. Collins ,  Craig A. Roderick ,  Chan-Lon Yang ,  David N. K. Wang ,  Dan Maydan

发明人： Kenneth S. Collins ,  Craig A. Roderick ,  Chan-Lon Yang ,  David N. K. Wang ,  Dan Maydan

IPC分类号： C23C16/509 ,  H01J37/32 ,  H05H1/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01J37/32174 ,  C23C16/509 ,  H01J37/32082 ,  H05H1/46

摘要： An improved method of fabricating integrated circuit structures on semiconductor wafers using a plasma-assisted process is disclosed wherein the plasma is generated by a VHF/UHF power source at a frequency ranging from about 50 to about 800 MHz. Low pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out within a pressure range not exceeding about 500 milliTorr; with a ratio of anode to cathode area of from about 2:1 to about 20:1, and an electrode spacing of from about 5 cm. to about 30 cm. High pressure plasma-assisted etching or deposition processes, i.e., processes may be carried out with a pressure ranging from over 500 milliTorr up to 50 Torr or higher; with an anode to cathode electrode spacing of less than about 5 cm. By carrying out plasma-assisted processes using plasma operated within a range of from about 50 to about 800 MHz, the electrode sheath voltages are maintained sufficiently low, so as to avoid damage to structures on the wafer, yet sufficiently high to preferably permit initiation of the processes without the need for supplemental power sources. Operating in this frequency range may also result in reduction or elimination of microloading effects.

摘要翻译： 公开了使用等离子体辅助方法制造半导体晶片上的集成电路结构的改进方法，其中等离子体由VHF / UHF电源以约50至约800MHz的频率产生。 低压等离子体辅助蚀刻或沉积工艺，即工艺可以在不超过约500毫托的压力范围内进行; 阳极与阴极面积的比例为约2:1至约20:1，电极间距约为5cm。 到约30厘米。 高压等离子体辅助蚀刻或沉积工艺，即工艺可以在500毫乇至50乇以上的压力下进行; 阳极至阴极间距小于约5厘米。 通过使用在约50至约800MHz的范围内操作的等离子体等离子体辅助处理，电极护套电压保持足够低，以避免损坏晶片上的结构，但足够高以优选允许引发 该过程无需补充电源。 在该频率范围内工作也可能导致微载物效应的降低或消除。

公开(公告)号：US08921206B2

公开(公告)日：2014-12-30

申请号：US13308513

申请日：2011-11-30

申请人： Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

发明人： Chan-Lon Yang ,  Ching-I Li ,  Ger-Pin Lin ,  I-Ming Lai ,  Yun-San Huang ,  Chin-I Liao ,  Chin-Cheng Chien

IPC分类号： H01L21/36

CPC分类号： H01L29/6656 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

摘要： First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C.

摘要翻译： 首先，在半导体工艺中设置具有凹部的基板。 第二，在衬底中形成嵌入的SiGe层。 嵌入的SiGe层包括填充凹槽的外延SiGe材料。 然后，在嵌入的SiGe层上进行预非晶化植入（PAI）工艺以形成非晶区域。 接下来，在嵌入的SiGe层上进行源极/漏极注入工艺以形成源极掺杂区域和漏极掺杂区域。 之后，进行源极/漏极退火处理以在衬底中形成源极和漏极。 前非晶化植入程序和源极/漏极注入程序中的至少一个在低于-30℃的低温过程中进行。

公开(公告)号：US08575043B2

公开(公告)日：2013-11-05

申请号：US13191430

申请日：2011-07-26

申请人： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

发明人： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

IPC分类号： H01L21/00 ,  B23K26/02 ,  B23K26/08

CPC分类号： H01L21/268 ,  H01L21/26586

摘要： A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an included angle.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括：通过在第一扫描方向上单独地发射第一激光，对半导体衬底进行第一退火处理，并且通过在第二扫描方向上单独地发射第二激光，对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有夹角。

公开(公告)号：US20130203226A1

公开(公告)日：2013-08-08

申请号：US13368006

申请日：2012-02-07

申请人： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

发明人： Chan-Lon Yang ,  Ching-Nan Hwang ,  Chi-Heng Lin ,  Chun-Yao Yang ,  Ger-Pin Lin ,  Ching-I Li

IPC分类号： H01L21/283 ,  H01L21/8234 ,  H01L21/762

CPC分类号： H01L28/24 ,  H01L21/26593 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0629 ,  H01L28/20

摘要： A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a forntside heating is different from a power for a backside heating.

摘要翻译： 提供半导体工艺，包括以下步骤。 在基板上形成多晶硅层。 对多晶硅层进行不对称双面加热处理，其中用于正面加热的功率不同于用于背面加热的功率。

公开(公告)号：US08404591B2

公开(公告)日：2013-03-26

申请号：US13482044

申请日：2012-05-29

申请人： Chiu-Hsien Yeh ,  Chan-Lon Yang ,  Chin-Cheng Chien ,  Lien-Fa Hung ,  Yun-Cheng Kao

发明人： Chiu-Hsien Yeh ,  Chan-Lon Yang ,  Chin-Cheng Chien ,  Lien-Fa Hung ,  Yun-Cheng Kao

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L29/517 ,  H01L21/31111 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/4966 ,  H01L29/513

摘要： A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution.

摘要翻译： 制造MOS器件的方法包括以下步骤：依次形成界面层，高k电介质层和衬底上的覆盖层。 然后，通过依次使用第一蚀刻溶液蚀刻覆盖层并使用第二蚀刻溶液来蚀刻高k电介质层和界面层直到基板被暴露来进行原位湿蚀刻步骤，其中第二蚀刻 溶液是含有第一蚀刻溶液的混合蚀刻溶液。

公开(公告)号：US20130026543A1

公开(公告)日：2013-01-31

申请号：US13191430

申请日：2011-07-26

申请人： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

发明人： Chan-Lon Yang ,  Tzu-Feng Kuo ,  Hsin-Huei Wu ,  Ching-I Li ,  Shu-Yen Chan

IPC分类号： H01L21/268 ,  H01L29/772

CPC分类号： H01L21/268 ,  H01L21/26586

摘要： A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle.

摘要翻译： 半导体器件包括设置在半导体衬底上的多个有源区。 半导体器件的制造方法包括：通过在第一扫描方向上单独地发射第一激光，对半导体衬底进行第一退火处理，并且通过在第二扫描方向上单独地发射第二激光，对半导体衬底进行第二退火处理。 第一扫描方向和第二扫描方向具有入射角。