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126 条记录 (耗时 0.028 秒)

    Electrostatic discharge protection circuit with variable limiting threshold for MOS device
    41.
    发明授权
    Electrostatic discharge protection circuit with variable limiting threshold for MOS device 失效
    MOS器件具有可变限流阈值的静电放电保护电路

    公开(公告)号：US4692834A

    公开(公告)日：1987-09-08

    申请号：US761707

    申请日：1985-08-02

    申请人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

    发明人： Hiroshi Iwahashi ,  Masamichi Asano ,  Akira Narita

    IPC分类号： H01L27/06 ,  H02H9/04 ,  H02H3/20

    CPC分类号： H02H9/046

    摘要： An electrostatic discharge protection circuit is provided with a variable threshold for limiting the potential of an input signal having a given high or low voltage, and is adapted to an EPROM containing an input MOS transistor which is responsive to the input signal. The protection circuit is associated with an input terminal for receiving the input signal. The input terminal is coupled to the gate of the input MOS transistor. The protection circuit also includes a circuit element for limiting or suppressing the input signal potential at the variable threshold. The gate of the input MOS transistor receives the potential limited signal from the circuit element. The circuit element is responsive to a given threshold control potential. The variable threshold is enhanced by the given threshold control potential when a high-voltage input signal is applied to the input terminal.

    摘要翻译： 静电放电保护电路具有用于限制具有给定高或低电压的输入信号的电位的可变阈值，并且适用于包含响应于输入信号的输入MOS晶体管的EPROM。 保护电路与用于接收输入信号的输入端相关联。 输入端耦合到输入MOS晶体管的栅极。 保护电路还包括用于限制或抑制在可变阈值处的输入信号电位的电路元件。 输入MOS晶体管的栅极接收来自电路元件的电位限制信号。 电路元件响应给定的阈值控制电位。 当将高电压输入信号施加到输入端时，通过给定的阈值控制电位增强可变阈值。

    Semiconductor memory with delay means to reduce peak currents
    42.
    发明授权
    Semiconductor memory with delay means to reduce peak currents 失效
    具有延迟的半导体存储器，以减少峰值电流

    公开(公告)号：US4556961A

    公开(公告)日：1985-12-03

    申请号：US379852

    申请日：1982-05-19

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： G11C5/06 ,  G11C8/14 ,  G11C11/40 ,  G11C7/00

    CPC分类号： G11C5/063 ,  G11C8/14

    摘要： A semiconductor device comprises a plurality of data supply circuits, output circuits for producing a plurality of data delivered from the data supply circuit and delay circuit for transferring respective data from each data supply circuit to a different output circuit with a different delay time. Each data supply circuit includes a plurality of row lines, a row decoder for selecting the row line in response to an address signal, a plurality of memory cell arrays including memory cells selectively driven by the row line and storing data, a plurality of column lines to receive data read out from the memory cell array, and a column decoder for selecting said column lines. The delay circuit prevents a plurality of data from being simultaneously outputted.

    摘要翻译： 半导体器件包括多个数据提供电路，用于产生从数据提供电路传送的多个数据的输出电路和用于将各个数据从每个数据提供电路传送到具有不同延迟时间的不同输出电路的延迟电路。 每个数据提供电路包括多行行，行解码器，用于响应于地址信号选择行行;多个存储单元阵列，包括由行行有选择地驱动并存储数据的存储单元;多个列线 以接收从存储单元阵列读出的数据，以及列解码器，用于选择所述列线。 延迟电路防止多个数据被同时输出。

    Semiconductor integrated circuit
    43.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US4542485A

    公开(公告)日：1985-09-17

    申请号：US337969

    申请日：1982-01-08

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： G05F3/24 ,  G11C5/00 ,  G11C5/14 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10 ,  G11C17/08 ,  G11C13/00 ,  G11C11/40

    CPC分类号： G11C5/147 ,  G05F3/242 ,  G11C17/08 ,  G11C5/00 ,  G11C7/22 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10

    摘要： A semiconductor integrated circuit comprises a first MOS transistor connected at the drain to a power source terminal of a high potential power source and supplied at the gate with a predetermined voltage, a logic circuit including MOS transistors provided between the power source terminal and a circuit point at a potential and operating in a potential range between the high potential and the circuit point, and a circuit for making the potential at the circuit point coincide with the potential at the source of the first MOS transistor.

    摘要翻译： 半导体集成电路包括：第一MOS晶体管，其在漏极处连接到高电位电源的电源端子，并在栅极处提供预定电压;逻辑电路，包括设置在电源端子与电路点之间的MOS晶体管 处于电位并且在高电位和电路点之间的电位范围内工作，并且用于使电路上的电位与第一MOS晶体管的源极处的电位一致的电路。

    Nonvolatile semiconductor memory device
    45.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4395724A

    公开(公告)日：1983-07-26

    申请号：US180435

    申请日：1980-08-22

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/02

    CPC分类号： H01L29/7881

    摘要： In a nonvolatile semiconductor memory device using as memory cells insulated-gate type field effect transistors each having source and drain regions, a floating gate electrode, and a control gate electrode, the width of the floating and control gate electrodes is narrower at those portions which are located over a channel between the source and drain regions in each memory cell than at those portions which are not located over the channel.

    摘要翻译： 在使用各自具有源极和漏极区域的存储单元绝缘栅型场效应晶体管的非易失性半导体存储器件中，浮置栅极电极和控制栅电极，浮动栅极电极和控制栅电极的宽度在 位于每个存储器单元中的源极和漏极区域之间的通道上，而不是位于通道上方的那些部分。

    Memory device utilizing MOS FETs
    46.
    发明授权
    Memory device utilizing MOS FETs 失效
    使用MOS FET的存储器件

    公开(公告)号：US4340943A

    公开(公告)日：1982-07-20

    申请号：US153951

    申请日：1980-05-28

    申请人： Masamichi Asano ,  Hiroshi Iwahashi

    发明人： Masamichi Asano ,  Hiroshi Iwahashi

    IPC分类号： G11C7/12 ,  G11C11/34 ,  G11C11/408 ,  G11C11/417 ,  G11C16/04 ,  G11C16/24 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C16/0416 ,  G11C11/4085 ,  G11C11/417 ,  G11C16/24 ,  G11C7/12

    摘要： A memory device utilizing metal oxide semiconductor field effect transistors (MOS FETs) formed in a semiconductor substrate. The memory device is so improved as to be accessed without a delay and as not to behave erroneously, in spite of a potential variation of data line or the semiconductor substrate. It comprises a plurality of row lines for supplying input signals, a plurality of column lines for supplying output signals, decoders for selecting any one of these lines, a plurality of memory cells connected to the row and column lines in a specific manner, a voltage sensing circuit connected to the column lines, a first potential source connected to the column lines, a second potential source for supplying the memory cells with a source voltage, and means for holding the column lines at a potential substantially equal to the voltage supplied from the second potential source when the potential of the column lines or the substrate varies.

    摘要翻译： 一种利用形成在半导体衬底中的金属氧化物半导体场效应晶体管（MOS FET）的存储器件。 尽管存在数据线或半导体衬底的潜在变化，存储器件如此改进以便无延迟地被访问并且不会出错。 它包括用于提供输入信号的多条行线，用于提供输出信号的多条列线，用于选择这些线中的任何一条的解码器，以特定方式连接到行和列线的多个存储单元，电压 连接到列线的感测电路，连接到列线的第一电位源，用于向存储器单元提供源极电压的第二电位源，以及用于将列线保持在基本上等于从 当列线或衬底的电位变化时，第二电位源。

    Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation
    47.
    发明授权
    Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation 失效
    具有在读取操作中防止高电压施加到存储器和虚设单元的传输门的半导体存储器件

    公开(公告)号：US5138579A

    公开(公告)日：1992-08-11

    申请号：US632613

    申请日：1990-12-26

    申请人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    发明人： Yuuichi Tatsumi ,  Hidenobu Minagawa ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Mizuho Imai

    IPC分类号： G11C7/00 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00

    CPC分类号： G11C16/28

    摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

    摘要翻译： 半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线 连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号 对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管 虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。 存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路 数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。

    Semiconductor memory device having a majority logic for determining data to be read out
    48.
    发明授权
    Semiconductor memory device having a majority logic for determining data to be read out 失效
    具有用于确定要读出的数据的多数逻辑的半导体存储器件

    公开(公告)号：US5067111A

    公开(公告)日：1991-11-19

    申请号：US426803

    申请日：1989-10-26

    申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

    发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Sadayuki Yokoyama

    IPC分类号： G06F11/18 ,  G11C16/26

    CPC分类号： G06F11/183 ,  G06F11/187 ,  G11C16/26

    摘要： A semiconductor memory device comprising a first Electrically Erasable Programmable Read Only Memory (EEPROM) cell array, a first row decoder, a first column decoder, two second EEPROM arrays each having a storage area equal in capacity to the specified storage area defined in the first EEPROM array, a second row decoder, a second column decoder, and a majority logic circuit. The first row decoder and the first column decoder access one of the memory cells of the first EEPROM array. The second row decoder and the second column decoder access one of the memory cells of either the second EEPROM array when one of the memory cells of first EEPROM array is accessed. The majority logic circuit carries out a majority logic operation on the data items read from the accessed memory cell of the first EEPROM array and the data items read from the accessed memory cells of the second EEPROM arrays, thereby to determine which data item is to be read out to an external device.

    摘要翻译： 一种半导体存储器件，包括第一电可擦除可编程只读存储器（EEPROM）单元阵列，第一行解码器，第一列解码器，两个第二EEPROM阵列，每个第二EEPROM阵列的容量等于在第一 EEPROM阵列，第二行解码器，第二列解码器和多数逻辑电路。 第一行解码器和第一列解码器访问第一EEPROM阵列的存储单元之一。 当访问第一EEPROM阵列的存储单元之一时，第二行解码器和第二列解码器访问第二EEPROM阵列中的一个存储器单元。 多数逻辑电路对从第一EEPROM阵列的访问存储单元读取的数据项和从第二EEPROM阵列的访问存储单元读取的数据项进行多数逻辑运算，从而确定哪个数据项将是 读出外部设备。

    Semiconductor memory device with a sense amplifier
    49.
    发明授权
    Semiconductor memory device with a sense amplifier 失效
    具有读出放大器的半导体存储器件

    公开(公告)号：US4799195A

    公开(公告)日：1989-01-17

    申请号：US168560

    申请日：1988-03-04

    申请人： Hiroshi Iwahashi ,  Masamichi Asano

    发明人： Hiroshi Iwahashi ,  Masamichi Asano

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C29/00 ,  G11C29/12 ,  G11C11/40

    CPC分类号： G11C16/28

    摘要： A semiconductor memory device comprises memory cell transistors each having a double layered gate having a floating gate and a control gate. The memory device comprises a transistor for receiving a predetermined voltage from a source external to the memory device and providing it as a reference voltage in response to a control signal, and a sense amplifier for comparing a voltage dependent on the data read from the memory cell with the reference voltage.

    摘要翻译： 半导体存储器件包括存储单元晶体管，每个存储单元晶体管具有一个具有浮置栅极和一个控制栅极的双层栅极。 存储器件包括晶体管，用于从存储器件外部的源接收预定电压并将其作为响应于控制信号的参考电压提供;以及读出放大器，用于根据从存储器单元读取的数据进行比较 具有参考电压。