公开(公告)号：US08110922B2

公开(公告)日：2012-02-07

申请号：US12588231

申请日：2009-10-08

Applicant: Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract translation: 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US07847416B2

公开(公告)日：2010-12-07

申请号：US12498913

申请日：2009-07-07

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US07830017B2

公开(公告)日：2010-11-09

申请号：US11950251

申请日：2007-12-04

Applicant: In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

Inventor： In-Young Lee ,  Dong-Ho Lee ,  Nam-Seog Kim ,  Hyun-Soo Chung ,  Ho-Jin Lee ,  Myeong-Soo Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract translation: 提供了其中在晶片级应用再分配处理的晶片级芯片级封装，其制造方法以及包括晶片级芯片级封装的半导体芯片模块。 晶片级芯片级封装包括具有接合焊盘的半导体芯片，设置在半导体芯片上以暴露焊盘的第一绝缘层，设置在暴露的焊盘和第一绝缘层上的再分配线，牺牲层 设置在所述再分配线的再分配衬垫的下方，设置在所述再分配线上的第二绝缘层，以暴露所述再分配衬垫并且包括设置在所述牺牲层旁边的裂纹诱导孔，以及附接到所述再分布衬垫的外部连接端子。

公开(公告)号：US07777345B2

公开(公告)日：2010-08-17

申请号：US12132925

申请日：2008-06-04

Applicant: Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Nam-Seog Kim ,  Yong-Chai Kwon ,  Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05561 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06136 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/00014

Abstract: A semiconductor device having a through electrode and a method of fabricating the same are disclosed. In one embodiment, a semiconductor device includes a first insulating layer formed on a semiconductor substrate. A wiring layer having a first aperture to expose a portion of the first insulating layer is formed on the first insulating layer. A second insulating layer is formed on an upper portion of the wiring layer and in the first aperture. A conductive pad having a second aperture to expose a portion of the second insulating layer is formed on the second insulating layer. A through hole with a width narrower than widths of the first and second apertures is formed through the first and second insulating layers and an upper portion of the semiconductor substrate. A through electrode is formed in the through hole.

Abstract translation: 公开了一种具有通孔的半导体器件及其制造方法。 在一个实施例中，半导体器件包括形成在半导体衬底上的第一绝缘层。 具有用于露出第一绝缘层的一部分的第一孔的布线层形成在第一绝缘层上。 第二绝缘层形成在布线层的上部和第一孔中。 具有第二孔径以暴露第二绝缘层的一部分的导电焊盘形成在第二绝缘层上。 通过第一和第二绝缘层和半导体衬底的上部形成宽度比第一和第二孔的宽度窄的通孔。 在通孔中形成贯通电极。

公开(公告)号：US07740145B2

公开(公告)日：2010-06-22

申请号：US10540566

申请日：2003-12-23

Applicant: Hyun-Soo Chung

Inventor： Hyun-Soo Chung

IPC: B65D39/12

CPC classification number: B65D49/04 ,  B65D49/00 ,  B65D55/12

Abstract: A bottle cap is disclosed, which displays an opened state and cannot contain contents again once it is opened. The bottle cap includes a cap having a screw formed on its inner surface to be engaged with a screw formed on an outer surface of a nozzle of a bottle, a reverse moving means connected to the cap and ascending in a direction opposite to a descending direction of the cap as the cap is rotated downwardly, a rod shaped nut having a screw engaged with the reverse moving means and moving up and down in a screw direction without rotation, and a display installed in the lower portion of the nut, displaying an opened state of the cap by hanging a part of the cap in the nozzle as the cap is moved downwardly by being pushed by the nut if the cap is opened.

Abstract translation: 公开了一种瓶盖，其显示打开的状态，并且一旦打开状态就不能再含有内容物。 瓶盖包括盖，该盖具有形成在其内表面上的螺钉，以与形成在瓶的喷嘴的外表面上的螺钉相接合;反向移动装置，连接到盖并沿与下降方向相反的方向上升 盖帽旋转向下旋转的杆状螺母，具有与反向移动装置接合的螺钉并沿螺钉方向上下移动而不旋转的杆形螺母，以及安装在螺母下部的显示器， 如果盖子被打开，当盖子通过被螺母推动而向下移动时，将盖子的一部分悬挂在喷嘴中。

公开(公告)号：US07544538B2

公开(公告)日：2009-06-09

申请号：US11775120

申请日：2007-07-09

Applicant: Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

Abstract: Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

Abstract translation: 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US20070269931A1

公开(公告)日：2007-11-22

申请号：US11752219

申请日：2007-05-22

Applicant: Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  In-Young Lee ,  Son-Kwan Hwang ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2224/11 ,  H01L2224/05552

Abstract: Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.

Abstract translation: 提供了晶片级封装及其制造方法。 在一个实施例中，方法之一包括形成在晶片上具有连接焊盘的半导体芯片，图案化晶片的底表面以在连接焊盘下方形成沟槽，图案化沟槽的底表面以形成通孔， 并且通过通孔形成连接到连接垫的连接装置。 本发明提供了与传统封装相比，具有减小的厚度，较低的制造成本和增加的可靠性的晶片级封装。

公开(公告)号：US20070246826A1

公开(公告)日：2007-10-25

申请号：US11585088

申请日：2006-10-24

Applicant: Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

Inventor： Hyun-Soo Chung ,  Seung-Duk Baek ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.

Abstract translation: 晶片级半导体模块可以包括安装在模块板上的模块板和IC芯片组。 IC芯片组可以包括在相邻IC芯片之间具有划线区域的多个IC芯片。 每个IC芯片可以具有具有多个芯片焊盘和后表面的有源表面的半导体衬底。 可以在每个IC芯片的半导体衬底的有源表面上提供钝化层，并且可以具有可以暴露芯片焊盘的开口。 密封部分可以形成在划线区域中。

公开(公告)号：US20070184577A1

公开(公告)日：2007-08-09

申请号：US11653862

申请日：2007-01-17

Applicant: Hyun-Soo Chung ,  Seong-Deok Hwang ,  Seung-Kwan Ryu ,  Dong-Ho Lee

Inventor： Hyun-Soo Chung ,  Seong-Deok Hwang ,  Seung-Kwan Ryu ,  Dong-Ho Lee

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of fabricating a wafer level package may include providing semiconductor substrate having a bonding pad; forming a passivation layer on the semiconductor substrate and partially exposing the boding pad, forming a first insulating layer on the passivation layer; forming a seed metal layer on the first insulating layer and the bond pad; forming a metal bump on a portion of the seed metal layer; forming a redistributing metal layer on the seed metal layer by melting the metal bump; forming a second insulating layer on the first insulating layer and the redistributing metal layer to expose a metal pad; and forming a conductive bump on the exposed metal pad.

Abstract translation: 制造晶片级封装的方法可以包括提供具有焊盘的半导体衬底; 在所述半导体衬底上形成钝化层，并部分地曝光所述焊盘，在所述钝化层上形成第一绝缘层; 在所述第一绝缘层和所述接合焊盘上形成种子金属层; 在种子金属层的一部分上形成金属凸块; 通过熔化金属凸块在种子金属层上形成再分布金属层; 在所述第一绝缘层和所述再分布金属层上形成第二绝缘层以暴露金属焊盘; 并在暴露的金属垫上形成导电凸块。