公开(公告)号：US20080254225A1

公开(公告)日：2008-10-16

申请号：US11735987

申请日：2007-04-16

申请人： William Thie ,  John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Parks ,  Tiruchirapalli Arunagiri ,  Aleksander Owczarz ,  Todd Balisky ,  Clint Thomas ,  Jacob Wylie

发明人： William Thie ,  John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Parks ,  Tiruchirapalli Arunagiri ,  Aleksander Owczarz ,  Todd Balisky ,  Clint Thomas ,  Jacob Wylie

IPC分类号： B05D1/18 ,  B05C13/00

CPC分类号： H01L21/02104 ,  C23C18/1619 ,  H01L21/67005 ,  H01L21/6715

摘要： A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.

摘要翻译： 半导体晶片化学镀设备包括压板和流体碗。 压板具有限定为支撑晶片的顶表面和从顶表面的周边向下延伸到压板的下表面的外表面。 流体碗具有由内表面限定的内部容积，以便在内部容积内容纳压板和要支撑在其上的晶片。 密封件设置在流体碗的内表面周围，以便当接合在流体碗的内表面和压板的外表面之间时形成液密屏障。 多个流体分配喷嘴被定位成在密封件上方的流体碗内分配电镀溶液，以便在压板上升起并流动，从而当存在于压板上时流过晶片。

公开(公告)号：US08069813B2

公开(公告)日：2011-12-06

申请号：US11735984

申请日：2007-04-16

申请人： William Thie ,  John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Parks ,  Tiruchirapalli Arunagiri ,  Aleksander Owczarz ,  Todd Balisky ,  Clint Thomas ,  Jacob Wylie ,  Alan M. Schoepp

发明人： William Thie ,  John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  John Parks ,  Tiruchirapalli Arunagiri ,  Aleksander Owczarz ,  Todd Balisky ,  Clint Thomas ,  Jacob Wylie ,  Alan M. Schoepp

IPC分类号： B05C3/00

CPC分类号： H01L21/288 ,  C23C18/1619 ,  C23C18/1632 ,  H01L21/76873

摘要： A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM).

摘要翻译： 公开了一种用于晶片无电镀的干/干输出系统。 该系统包括用于晶片入口/出口和干燥操作的上部区域。 靠近头部设置在上部区域以执行干燥操作。 该系统还包括用于无电镀操作的下部区域。 下部区域包括通过流体上升流法实现晶片浸没的化学镀设备。 系统的上部和下部区域由双壁室围住，其中内壁是化学惰性塑料，外壁是结构金属。 系统与流体处理系统接口，为系统提供必要的化学物质供应和控制。 系统是环境控制的。 此外，系统与环境受控的托管传输模块（MTM）接口。

公开(公告)号：US07396430B2

公开(公告)日：2008-07-08

申请号：US11395881

申请日：2006-03-31

申请人： John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  Michael Ravkin ,  John de Larios

发明人： John M. Boyd ,  Fritz C. Redeker ,  Yezdi Dordi ,  Michael Ravkin ,  John de Larios

IPC分类号： H01L21/306

CPC分类号： H01L21/32115 ,  C25F7/00

摘要： A proximity head and associated method of use is provided for performing confined area planarization of a semiconductor wafer. The proximity head includes a chamber defined to maintain an electrolyte solution. A cathode is disposed within the chamber in exposure to the electrolyte solution. A cation exchange membrane is disposed over a lower opening of the chamber. A top surface of the cation exchange membrane is in direct exposure to the electrolyte solution to be maintained within the chamber. A fluid supply channel is defined to expel fluid at a location adjacent to a lower surface of the cation exchange membrane. A vacuum channel is defined to provide suction at a location adjacent to the lower surface of the cation exchange membrane, such that the fluid to be expelled from the fluid supply channel is made to flow over the lower surface of the cation exchange membrane.

摘要翻译： 提供接近头和相关联的使用方法用于执行半导体晶片的限定区域平坦化。 邻近头包括限定为维持电解质溶液的室。 在室内暴露于电解质溶液中设置阴极。 阳离子交换膜设置在室的下部开口的上方。 阳离子交换膜的顶表面直接暴露于电解质溶液中以保持在室内。 流体供应通道被定义为在邻近阳离子交换膜的下表面的位置排出流体。 定义真空通道以在邻近阳离子交换膜的下表面的位置处提供吸力，使得要从流体供应通道排出的流体流过阳离子交换膜的下表面。

公开(公告)号：US07749893B2

公开(公告)日：2010-07-06

申请号：US11641361

申请日：2006-12-18

申请人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： Fritz Redeker ,  John Boyd ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763

CPC分类号： C25D7/123 ,  C23C18/1653 ,  C23C28/023 ,  C23C28/322 ,  C23C28/34 ,  C23C28/341 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to methods and systems for the metallization of semiconductor devices. One aspect of the present invention is a method of depositing a copper layer onto a barrier layer so as to produce a substantially oxygen free interface therebetween. In one embodiment, the method includes providing a substantially oxide free surface of the barrier layer. The method also includes depositing an amount of atomic layer deposition (ALD) copper on the oxide free surface of the barrier layer effective to prevent oxidation of the barrier layer. The method further includes depositing a gapfill copper layer over the ALD copper. Another aspect of the present invention is a system for depositing a copper layer onto barrier layer so as to produce a substantially oxygen-free interface therebetween. In one embodiment, the integrated system includes at least one barrier deposition module. The system also includes an ALD copper deposition module configured to deposit copper by atomic layer deposition. The system further includes a copper gapfill module and at least one transfer module coupled to the at least one barrier deposition module and to the ALD copper deposition module. The transfer module is configured so that the substrate can be transferred between the modules substantially without exposure to an oxide-forming environment.

摘要翻译： 本发明涉及用于半导体器件金属化的方法和系统。 本发明的一个方面是将铜层沉积在阻挡层上以在其间产生基本上无氧的界面的方法。 在一个实施例中，该方法包括提供阻挡层的基本上无氧化物的表面。 该方法还包括在阻挡层的无氧化物表面上沉积一定量的原子层沉积（ALD）铜，以有效地防止阻挡层的氧化。 该方法还包括在ALD铜上沉积间隙填充铜层。 本发明的另一方面是一种用于在阻挡层上沉积铜层以在其间产生基本上无氧的界面的系统。 在一个实施例中，集成系统包括至少一个阻挡层沉积模块。 该系统还包括配置为通过原子层沉积沉积铜的ALD铜沉积模块。 该系统还包括铜间隙填充模块和耦合到至少一个阻挡层沉积模块和ALD铜沉积模块的至少一个传输模块。 转移模块被配置为使得基板可以在基本上不暴露于氧化物形成环境的基础之间传递。

公开(公告)号：US20100108491A1

公开(公告)日：2010-05-06

申请号：US12683995

申请日：2010-01-07

申请人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

发明人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

IPC分类号： H05F3/00

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/67069 ,  H05H1/24 ,  H05H1/2406 ,  H05H1/48 ,  H05H2001/2418

摘要： A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.

摘要翻译： 提供了一种用于从衬底去除金属氧化物的等离子体的方法。 该方法包括提供一种动力电极组件，其包括供电电极，电介质层和布置在电源电极和电介质层之间的金属丝网。 该方法还包括提供与动力电极组件相对设置的接地电极组件，以形成其中产生等离子体的空腔。 当等离子体存在于空腔中时，金属丝网通过电介质层被屏蔽，等离子体在一端具有出口，用于提供等离子体以去除金属氧化物。 该方法还包括将至少一种惰性气体和至少一种工艺气体引入空腔中。 该方法还包括使用动力电极将空穴场施加到空腔，以从惰性气体和处理气体产生等离子体。

公开(公告)号：US07662253B2

公开(公告)日：2010-02-16

申请号：US11237457

申请日：2005-09-27

申请人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

发明人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/67069 ,  H05H1/24 ,  H05H1/2406 ,  H05H1/48 ,  H05H2001/2418

摘要： An apparatus generating a plasma for removing metal oxide from a substrate is disclosed. The embodiment includes a powered electrode assembly, including a powered electrode, a first dielectric layer, and a first wire mesh disposed between the powered electrode and the first dielectric layer. The embodiment also includes a grounded electrode assembly disposed opposite the powered electrode assembly so as to form a cavity wherein the plasma is generated, the first wire mesh being shielded from the plasma by the first dielectric layer when the plasma is present in the cavity, the cavity having an outlet at one end for providing the plasma to remove the metal oxide.

摘要翻译： 公开了一种从衬底生成用于去除金属氧化物的等离子体的装置。 该实施例包括动力电极组件，其包括供电电极，第一介电层和设置在电源电极和第一介电层之间的第一丝网。 该实施例还包括与动力电极组件相对设置的接地电极组件，以便形成其中产生等离子体的空腔，当等离子体存在于空腔中时，第一金属丝网被第一介电层与等离子体屏蔽， 空腔在一端具有出口，用于提供等离子体以去除金属氧化物。

公开(公告)号：US08883027B2

公开(公告)日：2014-11-11

申请号：US12683995

申请日：2010-01-07

申请人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

发明人： Hyungsuk Alexander Yoon ,  William Thie ,  Yezdi Dordi ,  Andrew D. Bailey, III

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/02 ,  H05H1/24 ,  H01L21/67 ,  H01L21/311 ,  C23C16/00

CPC分类号： H01L21/31116 ,  H01L21/02063 ,  H01L21/67069 ,  H05H1/24 ,  H05H1/2406 ,  H05H1/48 ,  H05H2001/2418

摘要： A method for generating plasma for removing metal oxide from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the metal oxide. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an rf field to the cavity using the powered electrode to generate the plasma from the inert and the process gas.

摘要翻译： 提供了一种用于从衬底去除金属氧化物的等离子体的方法。 该方法包括提供一种动力电极组件，其包括供电电极，电介质层和布置在电源电极和电介质层之间的金属丝网。 该方法还包括提供与动力电极组件相对设置的接地电极组件，以形成其中产生等离子体的空腔。 当等离子体存在于空腔中时，金属丝网通过电介质层被屏蔽，等离子体在一端具有出口，用于提供等离子体以去除金属氧化物。 该方法还包括将至少一种惰性气体和至少一种工艺气体引入空腔中。 该方法还包括使用动力电极将空穴场施加到空腔，以从惰性气体和处理气体产生等离子体。

公开(公告)号：US08323460B2

公开(公告)日：2012-12-04

申请号：US11820810

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： C25D17/00

CPC分类号： C25D3/00 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/67005 ,  H01L21/67023 ,  H01L21/67075 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/768 ,  H01L21/7684 ,  H01L21/76883 ,  H01L21/76898

摘要： Presented are methods and systems for fabricating three-dimensional integrated circuits having large diameter through-hole vias. One embodiment of the present invention provides a method of processing a wafer having holes for through-hole vias. The method comprises plating a gapfill metal on the wafer. The method also comprises chemically or electrochemically deplating a portion of the overburden metal. The method further comprises using chemical mechanical planarization to planarize the gapfill metal and to remove the remaining overburden metal. Another embodiment of the present invention is an integrated system comprising a process chamber for containing the wafer, a plating component integrated with the process chamber, and a deplating component integrated with the process chamber. The plating component is configured to electrochemically plate a gapfill metal onto the wafer to a least partially fill the holes. The deplating component is configured to chemically or to electrochemically remove a portion of the overburden metal formed by the plating component.

摘要翻译： 提出了用于制造具有大直径通孔的三维集成电路的方法和系统。 本发明的一个实施例提供一种处理具有用于通孔过孔的孔的晶片的方法。 该方法包括在晶片上镀覆间隙填充金属。 该方法还包括化学地或电化学地去除一部分覆盖层金属。 该方法还包括使用化学机械平面化来平坦化间隙填充金属并除去剩余的覆盖层金属。 本发明的另一实施例是一种集成系统，其包括用于容纳晶片的处理室，与处理室一体化的电镀部件，以及与处理室一体化的去掉部件。 电镀部件被配置为将间隙填充金属电化学地平板化到晶片上以至少部分地填充孔。 脱镀部件被配置为化学地或电化学地去除由电镀部件形成的覆盖层金属的一部分。

公开(公告)号：US08187968B2

公开(公告)日：2012-05-29

申请号：US12613518

申请日：2009-11-05

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/00

CPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L21/76898 ,  H01L2924/14

摘要： Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.

摘要翻译： 提出了制造三维集成电路的方法，其包括用于三维集成电路的集成的线路通孔的后接触后端。 本发明的另一方面包括根据本发明的方法制造的三维集成电路。

公开(公告)号：US08673769B2

公开(公告)日：2014-03-18

申请号：US11821051

申请日：2007-06-20

申请人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

发明人： John Boyd ,  Fritz Redeker ,  Yezdi Dordi ,  Hyungsuk Alexander Yoon ,  Shijian Li

IPC分类号： H01L21/4763

CPC分类号： H01L21/44 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatuses for fabricating three-dimensional integrated circuits having through hole vias are provided. One aspect of the present invention is a method of gapfill for through hole vias for three-dimensional integrated circuits. The method comprises providing a semiconductor wafer having a plurality of holes for through hole vias and depositing a conformal metal layer to partially fill the holes to leave open voids. The method also includes purging the voids and cleaning the surface of the voids and using a dry deposition process to fill or close the voids. Another aspect of the present invention is an electronic device structure for a three-dimensional integrated circuit.

摘要翻译： 提供了具有通孔的三维集成电路的制造方法和装置。 本发明的一个方面是用于三维集成电路的通孔通孔的间隙填充方法。 该方法包括提供具有用于通孔通孔的多个孔的半导体晶片，并且沉积保形金属层以部分填充孔以留下开孔。 该方法还包括清除空隙并清洁空隙的表面，并使用干式沉积工艺填充或封闭空隙。 本发明的另一方面是一种用于三维集成电路的电子设备结构。