公开(公告)号：US20190132006A1

公开(公告)日：2019-05-02

申请号：US16178901

申请日：2018-11-02

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Christian Badack ,  Michael Goessel

IPC: H03M13/15

Abstract: A circuit arrangement for determining in parallel of at least two byte error position signals for identifying at least one byte error in a binary sequence comprising a plurality of bytes, wherein the binary sequence in the error-free case is a code word of an error code, the circuit arrangement is configured such that each of the at least two byte error position signals is determinable using components of an error syndrome of the error code such that the components indicate whether or not a byte of the binary sequence that is associated with the byte error position signal is erroneous.

公开(公告)号：US10216573B2

公开(公告)日：2019-02-26

申请号：US15410912

申请日：2017-01-20

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/15 ,  H03M13/29 ,  G11C29/04

Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.

公开(公告)号：US10067826B2

公开(公告)日：2018-09-04

申请号：US15194089

申请日：2016-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/13 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/04

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

公开(公告)号：US20170046222A1

公开(公告)日：2017-02-16

申请号：US15232323

申请日：2016-08-09

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1044 ,  G11C17/146 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Abstract translation: 提出了一种用于存储存储器的存储单元中的位的方法，其中在两个连续的写入操作中，第一和第二存储单元以相同的地址被写入相同的存储器单元，而在第一写操作之后不擦除存储单元，其中第一次检查 位存储在另外的第一存储器单元中，并且第二校验位存储在另外的第二存储器单元中。 此外指定相应的装置。

公开(公告)号：US09520161B2

公开(公告)日：2016-12-13

申请号：US14834897

申请日：2015-08-25

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Karl Hofmann

IPC: G11C5/06 ,  G11C11/56 ,  G11C7/22 ,  G11C7/14 ,  G11C16/28

CPC classification number: G11C5/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/5642 ,  G11C16/28

Abstract: A method and associated apparatus to determine a reference value on the basis of a plurality of half reference values stored in memory cells is disclosed, wherein the plurality of half reference values are read from the memory cells, wherein a subset of half reference values is determined from the plurality of half reference values, and wherein the reference value is determined on the basis of the subset of half reference values.

Abstract translation: 公开了一种基于存储在存储器单元中的多个半参考值来确定参考值的方法和相关设备，其中从存储器单元读取多个半参考值，其中确定半参考值的子集 从所述多个半参考值中，并且其中所述参考值基于所述半参考值的子集来确定。

公开(公告)号：US20160306696A1

公开(公告)日：2016-10-20

申请号：US15194089

申请日：2016-06-27

Applicant: Infineon Technologies AG

Inventor： Thomas Rabenalt ,  Ulrich Backhausen ,  Thomas Kern ,  Michael Goessel

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/13

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

Abstract translation: 公开了一种用于访问非易失性存储器的方法和存储器控制器。 该方法包括读取非易失性存储器的第一存储器区域，确定第一存储器区域是否包含预定数据模式，其中预定数据模式对至少第一存储器区域确定的所得到的纠错数据没有影响。 该方法基于第一存储器区域中的预定数据模式的存在来评估非易失性存储器的第二存储器区域的数据状态，其中数据状态指示是否存在有效数据中的至少一个 第二存储器区域以及第二存储器区域是否可写入。

公开(公告)号：US20160172029A1

公开(公告)日：2016-06-16

申请号：US14570219

申请日：2014-12-15

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Karl Hofmann ,  Michael Goessel

IPC: G11C13/00 ,  G11C29/52 ,  G11C29/00 ,  G06F11/10 ,  G11C11/16 ,  G11C29/08

CPC classification number: G11C29/76 ,  G06F11/1048 ,  G06F11/106 ,  G11C7/04 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0033 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50016 ,  G11C29/52 ,  H03M13/3715

Abstract: A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells.

Abstract translation: 一种刷新具有存储单元的非易失性存储器的系统和方法。 该方法包括识别不满足数据保留测试的一个或多个存储器单元; 将一个或多个所识别的存储器单元从原始存储器地址重新映射到备用存储器地址; 并刷新所识别的存储器单元。

公开(公告)号：US20140173386A1

公开(公告)日：2014-06-19

申请号：US13720780

申请日：2012-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thomas Kern ,  Ulrich Backhausen ,  Thomas Rabenalt ,  Christian Badack ,  Michael Goessel

IPC: H03M13/15

CPC classification number: H03M13/152 ,  H03M13/1575 ,  H03M13/616

Abstract: A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′1, . . . , v′n relative to a codeword v=v1, . . . , vn, in particular 3-bit errors containing an adjacent 2-bit error (burst error). The circuitry comprises a syndrome generator and a decoder. A modified BCH is used wherein n′ column vectors of a first BCH code submatrix are paired as column vector pairs so that a componentwise XOR combination of the two column vectors of each column vector pair produces an identical column vector K that is different from all column vectors of the first BCH submatrix. A second BCH submatrix comprises corresponding column vectors as the third power, according to Galois field arithmetic, of the column vector in the first BCH submatrix. The syndrome generated by the syndrome generator can be checked against the columns of the first and second submatrices.

Abstract translation: 提出了用于校正可能错误的二进制字v'= v'1中的错误的电路。 。 。 ，v'n相对于码字v = v1，。 。 。 ，vn，特别是包含相邻2位错误（突发错误）的3位错误。 电路包括校正子发生器和解码器。 使用修改的BCH，其中第一BCH码子矩阵的n个列向量作为列向量对配对，使得每个列向量对的两个列向量的分量XOR组合产生与所有列不同的相同列向量K 第一个BCH子矩阵的向量。 第二BCH子矩阵包括根据第一BCH子矩阵中的列向量的伽罗瓦域算术的作为第三功率的相应的列向量。 可以针对第一和第二子矩阵的列检查由发生器产生的综合征。

公开(公告)号：US11892906B2

公开(公告)日：2024-02-06

申请号：US17392415

申请日：2021-08-03

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Thomas Rabenalt ,  Michael Goessel

IPC: G06F11/00 ,  G06F11/08 ,  G11C29/42 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

CPC classification number: G06F11/08 ,  G06F11/1012 ,  G11C29/18 ,  G11C29/42 ,  G11C29/4401

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

公开(公告)号：US20230267039A1

公开(公告)日：2023-08-24

申请号：US18159365

申请日：2023-01-25

Applicant: Infineon Technologies AG

Inventor： Thomas Kern ,  Michael Goessel ,  Alexander Klockmann ,  Thomas Rabenalt

IPC: G06F11/10

CPC classification number: G06F11/1068

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.