公开(公告)号：US20150380481A1

公开(公告)日：2015-12-31

申请号：US14844816

申请日：2015-09-03

Applicant: INTEL CORPORATION

Inventor： ANNALISA CAPPELLANI ,  VAN H. LE ,  GLENN A. GLASS ,  KELIN J. KUHN ,  STEPHEN M. CEA

IPC: H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02241 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/76 ,  H01L21/7624 ,  H01L21/76283 ,  H01L29/0603 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/7378 ,  H01L29/785 ,  H01L33/12 ,  H05K1/18

Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.

Abstract translation: 公开了用于将应变诱导半导体缓冲层转化为缓冲层的一个或多个位置处的电绝缘体的技术，从而允许上述器件层具有许多益处，其在一些实施例中包括由于生长而产生的那些 在应变诱导缓冲器上并具有埋入的电绝缘体层。 例如，在非平面集成晶体管电路的Fin和衬底之间具有埋入的电绝缘体层（最初用作制造上述有源器件层期间的应变诱导缓冲器）可以同时使得具有高的低掺杂Fin 移动性，期望的器件静电，以及消除或以其他方式减少衬底结泄漏。 此外，源极和漏极区域下的这种电绝缘体的存在可以进一步显着减少结漏电。 在一些实施例中，基本上整个缓冲层被转换成电绝缘体。

公开(公告)号：US20150311204A1

公开(公告)日：2015-10-29

申请号：US14739994

申请日：2015-06-15

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

Abstract translation: 公开了用于形成低接触电阻晶体管器件的技术。 p型锗层设置在p型源极/漏极区及其各自的接触金属之间，n型III-V半导体材料层设置在n型源极/漏极区及其各自的接触金属之间。 n型III-V族半导体材料层可以具有小的带隙（例如，<0.5eV）和/或以其它方式掺杂以提供期望的导电性，并且p型锗层可以例如用硼掺杂。 在III型V材料沉积在n型源极/漏极区域和锗覆盖的p型源极/漏极区域之后，可以执行回蚀工艺以利用n型和p型之间的高度差 区域自对准接触类型，并在p型区域上露出p型锗，并在n型区域上稀薄n型III-V材料。 这些技术可以用于平面和非平面晶体管架构。

公开(公告)号：US20200286996A1

公开(公告)日：2020-09-10

申请号：US16876528

申请日：2020-05-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/775 ,  H01L21/30 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20190189794A1

公开(公告)日：2019-06-20

申请号：US16283756

申请日：2019-02-23

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  HAROLD W. KENNEL

IPC: H01L29/78 ,  H01L29/12 ,  H01L29/775 ,  H01L29/66 ,  H01L27/088 ,  H01L29/205 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US20190189785A1

公开(公告)日：2019-06-20

申请号：US16326845

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L29/10 ,  H01L29/1025 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.

公开(公告)号：US20190157310A1

公开(公告)日：2019-05-23

申请号：US16306295

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA ,  MAURO J. KOBRINSKY ,  PATRICK MORROW

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/775

Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.

公开(公告)号：US20190043993A1

公开(公告)日：2019-02-07

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US20180248015A1

公开(公告)日：2018-08-30

申请号：US15754874

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  MARK R. BRAZIER ,  ANAND S. MURTHY ,  TAHIR GHANI ,  OWEN Y. LOH

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/517 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.

公开(公告)号：US20180197789A1

公开(公告)日：2018-07-12

申请号：US15576396

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  YING PANG ,  NABIL G. MISTKAWI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  HUANG-LIN CHAO

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/6681

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US20180151733A1

公开(公告)日：2018-05-31

申请号：US15575011

申请日：2015-06-19

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PATRICK H. KEYS ,  HAROLD W. KENNEL ,  RISHABH MEHANDRU ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/167 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/0603 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.