公开(公告)号：US10810079B2

公开(公告)日：2020-10-20

申请号：US16178528

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C29/42 ,  H03M13/09 ,  H03M13/00 ,  G11C11/401

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

公开(公告)号：US10680613B2

公开(公告)日：2020-06-09

申请号：US16146326

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Alexey Kostinsky ,  Nadav Bonen

IPC: H03K19/0175 ,  G06F3/06 ,  G06F13/16

Abstract: On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.

公开(公告)号：US10552285B2

公开(公告)日：2020-02-04

申请号：US15993245

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： James A. McCall ,  Kuljit S. Bains

IPC: G06F12/00 ,  G06F13/00 ,  G06F11/30 ,  G06F13/42 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50 ,  G11C7/04 ,  G11C29/46

Abstract: A memory subsystem manages memory I/O impedance compensation by the memory device monitoring a need for impedance compensation. Instead of a memory controller regularly sending a signal to have the memory device update the impedance compensation when a change is not needed, the memory device can indicate when it is ready to perform an impedance compensation change. The memory controller can send an impedance compensation signal to the memory device in response to a compensation flag set by the memory or in response to determining that a sensor value has changed in excess of a threshold.

公开(公告)号：US10146711B2

公开(公告)日：2018-12-04

申请号：US15196014

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Bill Nale ,  Kuljit S. Bains ,  George Vergis ,  Christopher E. Cox ,  James A. McCall ,  Chong J. Zhao ,  Suneeta Sah ,  Pete D. Vogt ,  John R. Goles

IPC: G06F13/16 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

公开(公告)号：US09881659B2

公开(公告)日：2018-01-30

申请号：US14866579

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Tomishima Shigeki ,  Kuljit S. Bains ,  Tomer Levy

IPC: G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12

Abstract: Technologies for clearing a page of memory include a memory device configured write a value to a block of memory cells in response to an activation signal. The memory device includes a row decoder responsive to a memory address to select a row of memory cells and a column decoder responsive to the activation signal to select one or more columns of memory cells. Additionally, a write driver of the memory device is configured to write a value to global input/output lines, which are connected to the selected memory cells in response to the activation signal and regardless of data received on a data input of the write driver.

公开(公告)号：US09804793B2

公开(公告)日：2017-10-31

申请号：US15277182

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G11C7/00 ,  G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C16/20

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US09659626B1

公开(公告)日：2017-05-23

申请号：US14998091

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Kuljit S. Bains ,  John B. Halbert

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4096

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

公开(公告)号：US20170140801A1

公开(公告)日：2017-05-18

申请号：US15360675

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Bruce A. Christenson ,  Kuljit S. Bains

IPC: G11C7/10 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

公开(公告)号：US20170063394A1

公开(公告)日：2017-03-02

申请号：US14998142

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains ,  Kjersten E. Criss

IPC: H03M13/09 ,  H03M13/00

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.

Abstract translation: 在存储器件执行管芯ECC的系统中，ECC对N位数据字进行二（N / 2）位段的操作，其中码矩阵具有对应的N个代码，可以作为第一 （N / 2）码的一部分和（N / 2）码的第二部分，分别计算数据字的第一和第二（N / 2）位段的第一和第二错误检查。 在代码矩阵中，代码矩阵的第一部分中的任何两个代码的按位XOR或代码矩阵的第二部分中的任何两个代码产生不在代码矩阵中的代码，或者在另一部分中 的代码矩阵。 因此，一个部分中的错误的双位错误导致在另一部分中切换位而不是产生三位错误。

公开(公告)号：US20160276015A1

公开(公告)日：2016-09-22

申请号：US15170606

申请日：2016-06-01

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定对存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。