公开(公告)号：US20190341351A1

公开(公告)日：2019-11-07

申请号：US16474026

申请日：2017-03-29

申请人： Intel Corporation

发明人： Robert Alan May ,  Islam A. Salama ,  Sri Ranga Sai Boyapati ,  Sheng Li ,  Kristof Darmawikarta ,  Robert L. Sankman ,  Amruthavalli Pallavi Alur

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

摘要： A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US10361121B2

公开(公告)日：2019-07-23

申请号：US15154493

申请日：2016-05-13

申请人： Intel Corporation

发明人： Kristof Darmawikarta ,  Sri Ranga Sai Boyapati

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48

摘要： Embodiments herein relate to a package using aluminum oxide as an adhesion and high-thermal conductivity layer with a buildup layer having a first side and a second side opposite the first side, a first trace applied to the first side of the buildup layer, an aluminum oxide layer coupled with the first trace and an exposed area of the first side of the buildup layer, a lamination buildup layer coupled with the aluminum oxide layer on a side of the aluminum oxide layer opposite the buildup layer, wherein the lamination buildup layer includes one or more vias to the trace, and a seed layer coupled with the lamination buildup layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170362684A1

公开(公告)日：2017-12-21

申请号：US15674184

申请日：2017-08-10

申请人： INTEL CORPORATION

发明人： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC分类号： C22C9/00 ,  H01L23/498 ,  H01L23/12 ,  H01L23/49

CPC分类号： C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

摘要： Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US09758845B2

公开(公告)日：2017-09-12

申请号：US14773108

申请日：2014-12-09

申请人： Intel Corporation

发明人： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC分类号： H05K1/09 ,  C22C9/00 ,  H01L23/12 ,  H01L23/49 ,  H01L23/498

CPC分类号： C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

摘要： Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US09735120B2

公开(公告)日：2017-08-15

申请号：US14138754

申请日：2013-12-23

申请人： INTEL CORPORATION

发明人： Qinglei Zhang ,  Sri Ranga Sai Boyapati

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00

摘要： In embodiments, a package assembly may include a die coupled with one or more conductive pads. A barrier layer may be directly coupled with and between the die and one or more of the conductive pads. The package assembly may further include a solder resist layer coupled with the die and the conductive pads, and one or more interconnects positioned at least partially within the solder resist layer and directly coupled with one or more of the conductive pads.

公开(公告)号：US09449923B2

公开(公告)日：2016-09-20

申请号：US14969406

申请日：2015-12-15

申请人： Intel Corporation

发明人： Sri Ranga Sai Boyapati ,  Qinglei Zhang

IPC分类号： H01L21/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/48 ,  H05K3/40 ,  H05K3/00

CPC分类号： H01L23/53238 ,  H01L21/486 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K3/002 ,  H05K3/4076 ,  H05K2201/2072 ,  H05K2203/1184 ,  H05K2203/1476 ,  H01L2924/00

摘要： Methods of forming anchor structures in package substrate microvias are described. Those methods and structures may include forming a titanium layer in an opening of a package substrate using a first deposition process, wherein the opening comprises an undercut region, and wherein the first conductive layer does not substantially form in an anchor region of the undercut region. The titanium layer may then be re-sputtered using a second deposition process, wherein the titanium layer is formed in the anchor region.

公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

申请人： Intel Corporation

发明人： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

摘要： Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11894324B2

公开(公告)日：2024-02-06

申请号：US17528049

申请日：2021-11-16

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Telesphor Kamgaing ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Eyal Fayneh ,  Ofir Degani ,  David Levy ,  Johanna M. Swan

IPC分类号： H01L23/66 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/66 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/19033

摘要： In-package radio frequency (RF) waveguides as high bandwidth chip-to-chip interconnects and methods for using the same are disclosed. In one example, an electronic package includes a package substrate, first and second silicon dies or tiles, and an RF waveguide. The first and second silicon dies or tiles are attached to the package substrate. The RF waveguide is formed in the package substrate and interconnects the first silicon die or tile with the second silicon die or tile.

公开(公告)号：US11854834B2

公开(公告)日：2023-12-26

申请号：US17677105

申请日：2022-02-22

申请人： Intel Corporation

发明人： Kristof Kuwawi Darmawikarta ,  Robert May ,  Sri Ranga Sai Boyapati ,  Srinivas V. Pietambaram ,  Chung Kwang Christopher Tan ,  Aleksandar Aleksov

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L21/4857 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838

摘要： Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.

公开(公告)号：US11552010B2

公开(公告)日：2023-01-10

申请号：US16603863

申请日：2017-05-12

申请人： Intel Corporation

发明人： Robert A. May ,  Andrew J. Brown ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta

IPC分类号： H01L23/498 ,  C07D413/12 ,  C08G73/16 ,  C08K3/22 ,  C08K3/38 ,  C08K5/548 ,  C08K13/02 ,  H01L21/48

摘要： The present disclosure is directed to systems and methods for providing a dielectric layer on a semiconductor substrate capable of supporting very high density interconnects (i.e., ≥100 IO/mm). The dielectric layer includes a maleimide polymer in which a thiol-terminated functional group crosslinks with an epoxy resin. The resultant dielectric material provides a dielectric constant of less than 3 and a dissipation factor of less than 0.001. Additionally, the thiol functional group forms coordination complexes with noble metals present in the conductive structures, thus by controlling the stoichiometry of epoxy to polyimide, the thiol-polyimide may beneficially provide an adhesion enhancer between the dielectric and noble metal conductive structures.