公开(公告)号：US20250113521A1

公开(公告)日：2025-04-03

申请号：US18478626

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Andrey Vyatskikh ,  Paul B. Fischer ,  Paul Killian Nordeen ,  Uygar E. Avci ,  Mahmut Sami Kavrik ,  Ande Kitamura ,  Kirby Maxey ,  Carl Hugo Naylor ,  Kevin P. O'Brien

IPC: H01L29/775 ,  H01L21/762

Abstract: A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by a diffusion bonding layer. The direct transfer of TMD monolayers can be repeated to create a stack of TMD monolayers. A stack of TMD monolayers can be used in a field effect transistor, such as a nanoribbon field effect transistor.

公开(公告)号：US12266729B2

公开(公告)日：2025-04-01

申请号：US17485162

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Nafees A. Kabir ,  Shriram Shivaraman ,  Seung Hoon Sung ,  Uygar E. Avci

IPC: H01L21/4763 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of fabricating an integrated circuit structure comprises depositing an oxide insulator layer over a substrate having fins. A gate trench is formed within the oxide insulator layer with the fins extending above a surface of the oxide insulator layer within the gate trench. A semiconducting oxide material is deposited to conformally cover the oxide insulator layer, including on top surfaces and sidewalls of both the gate trench and the fins. A gate material is deposited to conformally cover the semiconducting oxide material, including on top surfaces and sidewalls of both the gate trench and the fins. An angled etch is performed to remove the gate material selective to the semiconducting oxide material from sidewalls of the gate trench, but not from sidewalls of the fins.

公开(公告)号：US20250006839A1

公开(公告)日：2025-01-02

申请号：US18343203

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Dmitri Evgenievich Nikonov ,  Rachel A. Steinhardt ,  Pratyush P. Buragohain ,  John J. Plombon ,  Hai Li ,  Gauri Auluck ,  I-Cheng Tung ,  Tristan A. Tronic ,  Dominique A. Adams ,  Punyashloka Debashis ,  Raseong Kim ,  Carly Rogan ,  Arnab Sen Gupta ,  Brandon Holybee ,  Marko Radosavljevic ,  Uygar E. Avci ,  Ian Alexander Young ,  Matthew V. Metz

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66

Abstract: A transistor device may include a first perovskite gate material, a first perovskite ferroelectric material on the first gate material, a first p-type perovskite semiconductor material on the first ferroelectric material, a second perovskite ferroelectric material on the first semiconductor material, a second perovskite gate material on the second ferroelectric material, a third perovskite ferroelectric material on the second gate material, a second p-type perovskite semiconductor material on the third ferroelectric material, a fourth perovskite ferroelectric material on the second semiconductor material, a third perovskite gate material on the fourth ferroelectric material, a first source/drain metal adjacent a first side of each of the first semiconductor material and the second semiconductor material, a second source/drain metal adjacent a second side opposite the first side of each of the first semiconductor material and the second semiconductor material, and dielectric materials between the source/drain metals and the gate materials.

公开(公告)号：US12058849B2

公开(公告)日：2024-08-06

申请号：US17522225

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Kinyip Phoa ,  Mauro J. Kobrinsky ,  Tahir Ghani ,  Uygar E. Avci ,  Rajesh Kumar

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

CPC classification number: H10B12/312 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.

公开(公告)号：US11653502B2

公开(公告)日：2023-05-16

申请号：US16700782

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Uygar E. Avci

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  G11C11/22 ,  H01L27/1159 ,  H01L49/02 ,  H01L27/11507 ,  G11C5/06

CPC classification number: H01L27/1159 ,  G11C5/063 ,  G11C11/221 ,  G11C11/223 ,  H01L27/11507 ,  H01L28/55 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/785 ,  H01L29/78391

Abstract: A device is disclosed. The device includes a substrate that includes a base portion and a fin portion that extends upward from the base portion, an insulator layer on sides and top of the fin portion, a first conductor layer on a first side surface of the insulator layer, a second conductor layer on a second side surface of the insulator layer, and a ferroelectric layer on portions of a top surface of the base portion, a portion of the insulator layer below the first conductor layer, a side and top surface of the first conductor layer, a top surface of the insulator layer above the fin portion, a side and top surface of the second conductor layer, and a portion of the insulator layer below the second conductor layer. A word line conductor is on the top surface of the ferroelectric layer.

公开(公告)号：US11532439B2

公开(公告)日：2022-12-20

申请号：US16296085

申请日：2019-03-07

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Nazila Haratipour ,  Seung Hoon Sung ,  Ashish Verma Penumatcha ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: G11C16/10 ,  H01G7/06 ,  G11C11/22 ,  H01L27/108 ,  H01L49/02

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

公开(公告)号：US20220328663A1

公开(公告)日：2022-10-13

申请号：US17853036

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

公开(公告)号：US11107908B2

公开(公告)日：2021-08-31

申请号：US16306540

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Jasmeet S. Chawla ,  Christopher J. Wiegand ,  Kanwaljit Singh ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/775 ,  H01L29/10 ,  H01L29/739 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L21/285 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/47 ,  H01L29/78

Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.

公开(公告)号：US10916547B2

公开(公告)日：2021-02-09

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US10886286B2

公开(公告)日：2021-01-05

申请号：US16146938

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11514 ,  H01L27/11509 ,  G11C11/22 ,  H01L25/18 ,  H01L23/532 ,  H01L23/528

Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.