公开(公告)号：US10692753B2

公开(公告)日：2020-06-23

申请号：US16240304

申请日：2019-01-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/764 ,  H01L21/306 ,  H01L29/786 ,  H01L27/12 ,  H01L21/027 ,  H01L21/266

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US10424686B2

公开(公告)日：2019-09-24

申请号：US15981191

申请日：2018-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Kirk D. Peterson

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/028 ,  H01L31/0232 ,  H01L31/02 ,  G02B6/12 ,  H01P1/17 ,  H01P3/16

Abstract: Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

公开(公告)号：US10361123B2

公开(公告)日：2019-07-23

申请号：US15799862

申请日：2017-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/482 ,  H01L21/762 ,  H01L23/532 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L21/683 ,  H01L21/74

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming a first switch and a second switch in the device layer. An electrically-conducting connection is formed in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

公开(公告)号：US20180040509A1

公开(公告)日：2018-02-08

申请号：US15788536

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/768 ,  H01L21/74 ,  H01L21/762 ,  H01L23/482 ,  H01L29/06 ,  H01L27/12 ,  H01L21/683 ,  H01L23/532 ,  H01L29/10

Abstract: A method for fabricating a backside contact using a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, and a handle wafer. The method includes forming an electrically-conducting connection in a trench. The handle wafer is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is connected to the buried insulator layer such that the electrically-conducting connection contacts the final substrate.

公开(公告)号：US09887156B2

公开(公告)日：2018-02-06

申请号：US15234913

申请日：2016-08-11

Applicant: International Business Machines Corporation

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L21/46 ,  H01L23/528 ,  H01L21/768 ,  H01L21/762 ,  H01L21/683 ,  H01L23/522 ,  H01L27/12 ,  H01L29/06 ,  H01L23/485

CPC classification number: H01L23/528 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/0649 ,  H01L2221/68327 ,  H01L2221/68372

Abstract: A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.

公开(公告)号：US09728838B2

公开(公告)日：2017-08-08

申请号：US14687002

申请日：2015-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hanyi Ding ,  Mark D. Jaffe ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L21/76 ,  H01L23/52 ,  H01Q1/22 ,  H01L21/762 ,  H01Q9/16

CPC classification number: H01Q1/2283 ,  H01L21/76224 ,  H01L23/5227 ,  H01Q9/16

Abstract: Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.

公开(公告)号：US09633894B2

公开(公告)日：2017-04-25

申请号：US14963530

申请日：2015-12-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/266 ,  H01L21/764 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/76289 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0273 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

公开(公告)号：US09300272B2

公开(公告)日：2016-03-29

申请号：US14700744

申请日：2015-04-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC: H03H9/00 ,  H03H9/54 ,  H03H9/17 ,  H03H9/56 ,  H03H9/05 ,  H03H9/15 ,  H03H9/02

CPC classification number: H03H9/545 ,  H03H9/0547 ,  H03H9/171 ,  H03H9/173 ,  H03H9/56 ,  H03H2009/02204 ,  Y10T29/42

Abstract: Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter.

公开(公告)号：US09252733B2

公开(公告)日：2016-02-02

申请号：US14522676

申请日：2014-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Anthony K. Stamper ,  Randy L. Wolf

IPC: H03H9/64 ,  H03H3/08 ,  H03H9/05 ,  H03H9/10 ,  H01L41/09 ,  B81B7/00 ,  B81B7/02 ,  G06F17/50 ,  H03H9/48 ,  H03H9/54 ,  H01P1/205

CPC classification number: H03H3/04 ,  B81B7/008 ,  B81B7/02 ,  G06F17/5045 ,  H01L41/094 ,  H01L41/0973 ,  H03H3/08 ,  H03H9/0542 ,  H03H9/0547 ,  H03H9/1064 ,  H03H9/1092 ,  H03H9/48 ,  H03H9/542 ,  H03H9/6403 ,  H03H9/6423 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49156

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.

Abstract translation: 本文公开了可切换和/或可调滤波器，制造方法和设计结构。 形成滤波器的方法包括形成至少一个包括形成在压电基片上的多个电极的压电滤波器结构。 该方法还包括形成微电子机械结构（MEMS），该微机电结构（MEMS）包括形成在压电基板上方的MEMS光束，并且在致动时，MEMS光束通过使多个或多个之中的至少一个接触而使压电滤波器结构短路的位置 的电极。

公开(公告)号：US20150340273A1

公开(公告)日：2015-11-26

申请号：US14283984

申请日：2014-05-21

Applicant: International Business Machines Corporation

Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

IPC: H01L21/762 ,  G02B6/132 ,  G02B6/136 ,  H01L29/06 ,  G02B6/134

CPC classification number: H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

Abstract translation: 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。