公开(公告)号：US20180331096A1

公开(公告)日：2018-11-15

申请号：US15590627

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Ruqiang Bao ,  Hemanth Jagannathan ,  ChoongHyun Lee

IPC: H01L27/088 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/098

CPC classification number: H01L27/0886 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/82345 ,  H01L27/088 ,  H01L27/098

Abstract: A method of fabricating a plurality of field effect transistors with different threshold voltages, including forming a cover layer on a channel region in a first subset, forming a first sacrificial layer on two or more channel regions in a second subset, forming a second sacrificial layer on one of the two or more channel regions in the second subset, removing the cover layer from the channel region in the first subset, forming a first dummy dielectric layer on the channel region in the first subset, and forming a second dummy dielectric layer on the first dummy dielectric layer and the first sacrificial layer on the channel region in the second subset.

公开(公告)号：US20180315756A1

公开(公告)日：2018-11-01

申请号：US15806759

申请日：2017-11-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/82285 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0652 ,  H01L27/0658 ,  H01L27/0664 ,  H01L27/2454 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7827 ,  H01L29/78642

Abstract: Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：US10103147B1

公开(公告)日：2018-10-16

申请号：US15582905

申请日：2017-05-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Zhenxing Bi ,  Choonghyun Lee ,  Zheng Xu

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：US10074574B2

公开(公告)日：2018-09-11

申请号：US15828802

申请日：2017-12-01

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924

Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.

公开(公告)号：US20180212040A1

公开(公告)日：2018-07-26

申请号：US15918199

申请日：2018-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/324 ,  H01L29/423

CPC classification number: H01L29/66553 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/324 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

公开(公告)号：US10020254B1

公开(公告)日：2018-07-10

申请号：US15727956

申请日：2017-10-09

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Joe Lee ,  Yann Mignot ,  Hosadurga Shobha ,  Junli Wang ,  Yongan Xu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76879 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: Semiconductor devices including super via structures and BEOL processes for forming the same, according to embodiments of the invention, generally include removing selected portions of a nitride cap layer intermediate interconnect levels, wherein the selected portions correspond to the regions where the super via structure is to be formed and where underlying overlay alignment markers are located.

公开(公告)号：US10002937B2

公开(公告)日：2018-06-19

申请号：US15176902

申请日：2016-06-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L21/306 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/30608 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of forming the same include forming a work function stack over semiconductor fins in a first region and a second region, the work function stack having a bottom layer, a middle layer, and a top layer. The work function stack is etched to remove the top layer and to decrease a thickness of the middle layer in the second region, leaving a portion of the middle layer and the bottom layer intact. A gate is formed over the semiconductor fins in the first and second regions.

公开(公告)号：US20180083017A1

公开(公告)日：2018-03-22

申请号：US15823022

申请日：2017-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8258 ,  H01L27/02

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US20180083016A1

公开(公告)日：2018-03-22

申请号：US15787768

申请日：2017-10-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8258

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.

公开(公告)号：US20180083015A1

公开(公告)日：2018-03-22

申请号：US15616131

申请日：2017-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Dechao Guo ,  Derrick Liu ,  Huimei Zhou

IPC: H01L27/11 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8258 ,  H01L21/8234 ,  H01L27/02

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11529 ,  H01L29/42376 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7855

Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.