公开(公告)号：US20090164677A1

公开(公告)日：2009-06-25

申请号：US12258680

申请日：2008-10-27

申请人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

发明人： Frederick A. Ware ,  Ian Shaeffer ,  Scott C. Best ,  Craig E. Hampel

IPC分类号： G06F1/04 ,  G06F13/00

CPC分类号： G06F13/4243

摘要： This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance.

摘要翻译： 本公开提供了一种用于在可重构存储器系统中调整系统定时的方法。 在动态点对点（“DPP”）系统中，例如，制造商提供的系统定时参数，例如访问延迟和最大时钟速度通常反映最坏情况的配置方案。 通过原位检测实际配置（例如，是否插入了扩展板），并且相应地将系统配置为以特定配置的方式运行，可能排除最坏情况或接近最坏情况的情况，系统时序 可以重新定义参数以达到比常规级别更高的性能; DPP系统尤其如此，其中信号路径通常随着附加模块的添加而变得更直接。 因此，与惯例智慧相反，这可能决定组件扩展应该减慢时序，如果配置支持，这样的系统实际上可以增加时钟速度，以获得更好的性能。

公开(公告)号：US20070247961A1

公开(公告)日：2007-10-25

申请号：US11768107

申请日：2007-06-25

申请人： Ian Shaeffer ,  Bret Stott ,  Benedict Lau

发明人： Ian Shaeffer ,  Bret Stott ,  Benedict Lau

IPC分类号： G11C8/00

CPC分类号： G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

摘要： A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

摘要翻译： 具有时间交错请求信号输出的存储器控​​制器。 根据第一编程值产生相对于第一时钟信号的相位偏移的第一定时信号，并且根据第二编程值产生相对于第一时钟信号的相位偏移的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

公开(公告)号：US20070162668A1

公开(公告)日：2007-07-12

申请号：US11292407

申请日：2005-11-30

申请人： Ian Shaeffer

发明人： Ian Shaeffer

IPC分类号： G06F13/12

CPC分类号： G11C8/16 ,  G06F12/00 ,  G06F13/4018 ,  G06F13/4243 ,  G11C8/06

摘要： Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

摘要翻译： 描述的是使用固定宽度内存模块支持动态点对点可扩展性的内存模块。 存储器模块包括数据宽度转换器，其允许模块改变其外部存储器接口的有效宽度，而不改变在转换器和相关联的固定宽度管芯之间延伸的内部存储器接口的宽度。 数据宽度转换器使用数据掩码信号来选择性地阻止对物理地址子集的存储器访问。 该数据屏蔽将物理地址位置划分为物理地址位置的两个或更多个时间子集，从而有效地增加给定模块中唯一可寻址位置的数量。 以写入顺序读取时间地址可能会引入不期望的读取延迟。 一些实施例重新排序读取数据以减少该等待时间。

公开(公告)号：US09966142B2

公开(公告)日：2018-05-08

申请号：US12990945

申请日：2009-05-06

申请人： Brent S. Haukness ,  Ian Shaeffer ,  Gary B. Bronner

发明人： Brent S. Haukness ,  Ian Shaeffer ,  Gary B. Bronner

IPC分类号： G06F12/00 ,  G11C16/10 ,  G06F3/06

CPC分类号： G11C16/10 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688

摘要： A memory system (100B) includes an array of non-volatile memory cells (140) and a memory controller (110) having a first port (port connected to line 101) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

公开(公告)号：US09176908B2

公开(公告)日：2015-11-03

申请号：US13578736

申请日：2010-11-23

申请人： Ian Shaeffer

发明人： Ian Shaeffer

IPC分类号： G06F13/16

CPC分类号： G06F13/1694 ,  G06F13/287 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4234

摘要： A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

摘要翻译： 存储器控制器通过使用时分复用总线来访问以不同本机速率运行的不同类型的存储器件。 当访问一种类型的存储设备时，以一种速率通过总线传送数据，并且在访问另一种类型的存储设备时以不同的速率传输数据。 此外，存储器控制器可以以不同的速率向不同类型的存储器件提供控制信息（例如，命令和地址信息），并且在一些情况下，将共享总线上的控制信息进行时间复用。

公开(公告)号：US08988102B2

公开(公告)日：2015-03-24

申请号：US13984825

申请日：2012-01-20

申请人： Ian Shaeffer

发明人： Ian Shaeffer

IPC分类号： H03K19/0175 ,  G11C7/00 ,  G11C5/06 ,  G11C7/10

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

摘要： Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

摘要翻译： 用于实现高速信令链路终止的本地片上终端控制器同时在布置在同一存储器模块上的多个集成电路存储器装置内和/或在相同的集成电路封装内并联耦合 到高速信令链路。 终端控制总线耦合到模块上的存储器件，并提供端对端控制信号的对等通信。

公开(公告)号：US08645617B2

公开(公告)日：2014-02-04

申请号：US13126726

申请日：2009-10-15

申请人： Ian Shaeffer ,  Brent Steven Haukness

发明人： Ian Shaeffer ,  Brent Steven Haukness

IPC分类号： G06F12/00

CPC分类号： G11C16/26 ,  G11C16/10 ,  G11C2216/22

摘要： This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices.

摘要翻译： 本公开提供了一种非易失性存储器设备，其同时处理涉及相同存储器空间的多页读取，擦除或写入。 该设备依赖于交叉开关和一组页面缓冲器，每个页面缓冲区可以动态分配给每个读取或写入请求。 该器件还将存储器阵列控制与IO控制分离，使得可以执行多个周期状态改变操作，同时缓冲器用于沿着外部数据总线将数据传入和传出缓冲器; 使用这种结构，存储器件可以接受多个事务，其中页面可以被立即加载到缓冲器中，然后“流水线化”以适当地传送到写数据寄存器或外部总线。 通过显着减轻与非易失性存储器件，特别是闪存器件的编程和擦除相关的实质性“繁忙时间”，本发明大大扩展了这种器件的潜在应用。

公开(公告)号：US20140002131A1

公开(公告)日：2014-01-02

申请号：US13984825

申请日：2012-01-20

申请人： Ian Shaeffer

发明人： Ian Shaeffer

IPC分类号： H03K19/0175

CPC分类号： H03K19/0005 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4063 ,  G11C11/413 ,  G11C16/06 ,  H03K19/017545

摘要： Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.

摘要翻译： 用于实现高速信令链路终止的本地片上终端控制器同时在布置在同一存储器模块上的多个集成电路存储器装置内和/或在相同的集成电路封装内并联，并耦合 到高速信令链路。 终端控制总线耦合到模块上的存储器件，并提供端对端控制信号的对等通信。

公开(公告)号：US20130314968A1

公开(公告)日：2013-11-28

申请号：US13983998

申请日：2012-02-07

申请人： Ian Shaeffer ,  Ravindranath Kollipara

发明人： Ian Shaeffer ,  Ravindranath Kollipara

IPC分类号： G11C5/02 ,  H01L23/48

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H01L23/3128 ,  H01L23/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00013 ,  H05K1/181 ,  H05K2201/10159 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： The disclosed embodiments relate to the design of a memory system which includes a set of one or more memory modules, wherein each memory module in the set has a clamshell configuration, wherein pairs of opposing memory packages containing memory chips are located on opposite sides of the memory module. The memory system also includes a multi-drop path containing signal lines which pass through the set of memory modules, and are coupled to memory packages in the set of memory modules. For a given signal line in the multi-drop path, a first memory package and a second memory package that comprise a given pair of opposing memory packages are coupled to the given signal line at a first location and a second location, respectively, wherein the first location and the second location are separated from each other by a distance d1 along the given signal line.

摘要翻译： 所公开的实施例涉及包括一组一个或多个存储器模块的存储器系统的设计，其中该组中的每个存储器模块具有蛤壳式配置，其中包含存储器芯片的对相对存储器组的对位于 内存模块 存储器系统还包括一个包含通过该组存储器模块的信号线的多点路径，并且耦合到该组存储器模块中的存储器封装。 对于多分支路径中的给定信号线，包括给定的一对相对的存储器封装的第一存储器封装和第二存储器封装分别在第一位置和第二位置耦合到给定的信号线，其中， 第一位置和第二位置沿着给定信号线彼此分开一段距离d1。

公开(公告)号：US20130138882A1

公开(公告)日：2013-05-30

申请号：US13814917

申请日：2011-08-04

申请人： Ian Shaeffer ,  Brent S. Haukness

发明人： Ian Shaeffer ,  Brent S. Haukness

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/344

摘要： A method of programming data into a memory device including an array of memory cells is disclosed. The method comprises receiving at least one program command that addresses a number of the memory cells for a programming operation to program data in the memory cells. The at least one program command is executed by iteratively carrying out at least one program/verify cycle to incrementally program the addressed memory cells with the program data. A secondary command may be selectively received after initiating but before completing the programming operation. The programming operation may be selectively resumed by first verifying the memory cells, then carrying out at least one program/verify cycle.

摘要翻译： 公开了一种将数据编程到包括存储器单元阵列的存储器件中的方法。 该方法包括接收至少一个编程命令，该程序命令寻址用于编程操作的多个存储器单元，以对存储器单元中的数据进行编程。 通过迭代地执行至少一个程序/验证周期来执行至少一个程序命令，以使用程序数据递增地编程所寻址的存储器单元。 可以在启动之后但在完成编程操作之前选择性地接收辅助命令。 可以通过首先验证存储器单元然后执行至少一个程序/验证周期来选择性地恢复编程操作。