公开(公告)号：US20210216238A1

公开(公告)日：2021-07-15

申请号：US17214770

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Bill NALE ,  George VERGIS

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a register clock driver (RCD) semiconductor chip having first inputs to receive first command and address (CA) signals from a first sub-channel and first outputs to drive first and second instances of the CA information that are decoded from the first CA signals. The RCD semiconductor chip has second inputs to receive second command and address (CA) signals from a second sub-channel. The RCD semiconductor chip has a multiplexer having a first input channel to receive the first CA signals and a second input channel to receive the second CA signals. The RCD semiconductor chip has second outputs to drive third and fourth instances of the first CA information or first and second instances of the second CA information that are decoded from the second CA signals depending on which of the first and second input channels of the multiplexer is selected.

公开(公告)号：US20210020224A1

公开(公告)日：2021-01-21

申请号：US17062420

申请日：2020-10-02

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20210005234A1

公开(公告)日：2021-01-07

申请号：US17030107

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Duane E. GALBI ,  Bill NALE

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G06F13/28 ,  G06F13/16

Abstract: An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module.

公开(公告)号：US20200176072A1

公开(公告)日：2020-06-04

申请号：US16781502

申请日：2020-02-04

Applicant: Intel Corporation

Inventor： Bill NALE

IPC: G11C29/46 ,  G06F11/30 ,  G11C29/44 ,  G11C29/02 ,  G06F11/32 ,  G11C29/00

Abstract: Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in SelfTest (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started.

公开(公告)号：US20190392886A1

公开(公告)日：2019-12-26

申请号：US16340084

申请日：2017-10-30

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Kuljit S. BAINS ,  Christopher P. MOZAK ,  James A. McCALL ,  Akshith VASANTH ,  Bill NALE

IPC: G11C11/4072 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4076

Abstract: A memory subsystem triggers entry and exit of a memory device from low power mode with a chip select (CS) signal line. For a system where the command bus has no clock enable (CKE) signal line, the system can trigger low power modes with CS instead of CKE. The low power mode can include a powerdown state. The low power mode can include a self-refresh state. The memory device includes an interface to the command bus, and receives a CS signal combined with command encoding on the command bus to trigger a low power mode state change. The memory device can be configured to monitor the CS signal and selected other command signals while in low power mode. The system can send an ODT trigger while the memory device is in low power mode, even without a dedicated ODT signal line.

公开(公告)号：US20190103154A1

公开(公告)日：2019-04-04

申请号：US15721052

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Christopher E. COX ,  Bill NALE

IPC: G11C11/4076 ,  G11C11/409 ,  G11C7/22 ,  G06F12/06

CPC classification number: G11C11/4076 ,  G06F12/0623 ,  G06F12/0646 ,  G06F13/1673 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/06 ,  G11C11/409

Abstract: A system provides a mailbox communication register for communication between a host and a mode register. The mode register is to store configuration information, and write of configuration information to the mode register by the host takes less time than a read of the configuration information from the mode register by the host. The communication register is separate from the mode register and provides a location to store the configuration information for a read by the host. In response to a read request by the host, the mode register can copy the configuration information to the communication register and allow the host to read the register based on different timing rules than those that apply to the mode register. Instead of reading directly from a register that has timing variance between read and write, the host can read from a communication register.

公开(公告)号：US20180210787A1

公开(公告)日：2018-07-26

申请号：US15540798

申请日：2017-05-02

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Bill NALE ,  Rajat AGARWAL

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/4093

Abstract: A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2̂N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.

公开(公告)号：US20170285941A1

公开(公告)日：2017-10-05

申请号：US15089455

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Bill NALE ,  Pete D. VOGT

IPC: G06F3/06

CPC classification number: G06F13/16 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0631 ,  G06F3/0685 ,  G06F13/1678 ,  G06F13/4018 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10

Abstract: A system includes a repeater architecture for reads where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.

公开(公告)号：US20160211973A1

公开(公告)日：2016-07-21

申请号：US15080580

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jonathan C. JASPER ,  Jun ZHU ,  Tuan M. QUACH

IPC: H04L9/08 ,  G06F13/16 ,  G11C7/10 ,  G06F13/42

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus method and apparatus for scrambling read data in a memory module. A read data packet having scrambled read data returned in response to a read request is received. The scrambler seed is updated in response to receiving the read data packet. The scrambler seed is used to descramble the scrambled read data.

Abstract translation: 提供了一种用于扰乱存储器模块中的读取数据的方法和装置方法和装置。 接收到响应读取请求返回的具有加扰读取数据的读取数据分组。 响应于接收到读取的数据分组来更新加扰器种子。 加扰器种子用于解扰加扰的读取数据。

公开(公告)号：US20160179604A1

公开(公告)日：2016-06-23

申请号：US15058129

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jun ZHU ,  Tuan M. QUACH

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for using an error signal to indicate a write request error and write request acceptance performing error handling operations using error signals. A memory module controller detects a write error for a write request in a memory module and asserts an error signal on a bus to a host memory controller in response to detecting the write error.

Abstract translation: 提供了一种使用误差信号来指示写请求错误和使用误差信号执行错误处理操作的写请求接受的方法和装置。 存储器模块控制器检测存储器模块中的写入请求的写入错误，并且响应于检测到写入错误，将总线上的错误信号断言到主机存储器控制器。