公开(公告)号：US11031359B2

公开(公告)日：2021-06-08

申请号：US16462197

申请日：2017-11-20

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC分类号： H01R9/00 ,  H01L23/64 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

摘要： A capacitor loop substrate assembly may include a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects may be formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US10964677B2

公开(公告)日：2021-03-30

申请号：US15845492

申请日：2017-12-18

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Seok Ling Lim ,  Kooi Chi Ooi

IPC分类号： H01L25/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/492 ,  H01L23/538 ,  H01L23/367 ,  H01L23/13 ,  H01L23/16 ,  H01L23/50 ,  H01L23/36 ,  H01L23/498 ,  H05K1/18

摘要： A semiconductor package apparatus includes a passive device that is embedded in a bottom package stiffener, and a top stiffener is stacked above the bottom package stiffener. Electrical connection through the passive device is accomplished through the stiffeners to a semiconductor die that is seated upon an infield region of the semiconductor package substrate.

公开(公告)号：US10903155B2

公开(公告)日：2021-01-26

申请号：US16402553

申请日：2019-05-03

申请人： Intel Corporation

发明人： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

IPC分类号： H01L23/498 ,  H01L23/66 ,  H01L23/552 ,  H01L23/00 ,  H01L25/18

摘要： Disclosed embodiments include a stacked multi-chip package that includes two semiconductor package substrates that are spaced apart by a vertical-device stiffener. The vertical-device stiffener provides both connection space for at least one vertical semiconductive device and at least one vertical radio-frequency device, as well as stiffness and form-factor reduction.

公开(公告)号：US20190244883A1

公开(公告)日：2019-08-08

申请号：US16341963

申请日：2016-11-18

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Seok Ling Lim

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19101 ,  H05K1/117 ,  H05K3/3405 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K2201/09536 ,  H05K2201/0959

摘要： An apparatus is provided which comprises: a plurality of organic dielectric layers forming a substrate, a plurality of first conductive contacts on a top surface of the substrate, a plurality of second conductive contacts on a bottom surface of the substrate, a plurality of third conductive contacts on a side wall surface of the substrate, and one or more discrete capacitor(s) coupled with the third conductive contacts on the side wall surface. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190006356A1

公开(公告)日：2019-01-03

申请号：US15988958

申请日：2018-05-24

申请人： Intel Corporation

发明人： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Hon Wah Chew

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L49/02

摘要： An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.

公开(公告)号：US09159714B2

公开(公告)日：2015-10-13

申请号：US14040642

申请日：2013-09-28

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Choong Kooi Chee ,  Seok Ling Lim

IPC分类号： H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

CPC分类号： H01L25/18 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/9222 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/014

摘要： An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points.

摘要翻译： 一种包括模具的设备，包括器件侧和相对的后侧，在后侧上的第一接触和从器件侧到第一接触件的通孔和在管芯的背面上的第二接触件或在管芯的至少两个相对的侧壁上 ; 耦合到所述第一多个触点的次模; 以及载体，其包括可操作用于将载体安装到基底的载体接触点。 一种方法，包括在模具的装置侧附近形成载体的第一部分，并且包括可操作以将载体安装到基底的载体接触点; 以及形成第二部分，所述第二部分包括连接到所述管芯的背面上的接触点或所述管芯的至少两个相对的侧壁上的第二载体接触点; 以及将次级管芯耦合到第二载体接触点。

公开(公告)号：US11574877B2

公开(公告)日：2023-02-07

申请号：US17088606

申请日：2020-11-04

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC分类号： H01L23/00 ,  H01L23/16 ,  H01L21/48 ,  H01L23/498

摘要： According to various examples, a device is described. The device may include a stiffener member including a first step section and a second step section. The device may also include a plurality of vias extending from or through the stiffener member. The device may be coupled to a printed circuit board.

公开(公告)号：US11476198B2

公开(公告)日：2022-10-18

申请号：US17024182

申请日：2020-09-17

申请人： Intel Corporation

发明人： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kok Keng Wan

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/50 ,  H01L21/60

摘要： Disclosed embodiments include multi-level fan-out integrated-circuit package substrates that provide a low-loss path to active and passive devices, by shunting away from interconnects and inductive loops. The multi-level form factor of a molded mass, allows for the low-loss path.

公开(公告)号：US20220302033A1

公开(公告)日：2022-09-22

申请号：US17631254

申请日：2020-06-26

申请人： Intel Corporation

发明人： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

摘要： Disclosed embodiments include silicon interconnect bridges that are in a molded frame, where the molded frame includes passive devices and the silicon interconnect bridge includes through-silicon vias that couple to a redistribution layer on both the silicon interconnect bridge and the molded frame.

公开(公告)号：US20220278084A1

公开(公告)日：2022-09-01

申请号：US17638039

申请日：2020-06-26

申请人： Intel Corporation

发明人： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC分类号： H01L25/16 ,  H01L23/538 ,  H01L49/02 ,  H01L25/00

摘要： Disclosed embodiments include molded interconnect bridges that are in a molded frame, where the molded frame includes passive devices that couple to a metal buildup layer that includes at least one power rail and one ground rail. The molded interconnects bridge is embedded in an integrated-circuit package substrate between a die side and a land side, and closer to the die side.