公开(公告)号：US20120292705A1

公开(公告)日：2012-11-22

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US20120280290A1

公开(公告)日：2012-11-08

申请号：US13102073

申请日：2011-05-06

申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/1104 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

公开(公告)号：US20120256260A1

公开(公告)日：2012-10-11

申请号：US13082491

申请日：2011-04-08

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66742 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78648

摘要： Doped semiconductor back gate regions self-aligned to active regions are formed by first patterning a top semiconductor layer and a buried insulator layer to form stacks of a buried insulator portion and a semiconductor portion. Oxygen is implanted into an underlying semiconductor layer at an angle so that oxygen-implanted regions are formed in areas that are not shaded by the stack or masking structures thereupon. The oxygen implanted portions are converted into deep trench isolation structures that are self-aligned to sidewalls of the active regions, which are the semiconductor portions in the stacks. Dopant ions are implanted into the portions of the underlying semiconductor layer between the deep trench isolation structures to form doped semiconductor back gate regions. A shallow trench isolation structure is formed on the deep trench isolation structures and between the stacks.

摘要翻译： 通过首先构图顶部半导体层和掩埋绝缘体层来形成与有源区域自对准的掺杂半导体背栅极区域，以形成埋入绝缘体部分和半导体部分的堆叠。 将氧气以一定角度注入到下面的半导体层中，使得注氧区域形成在不被叠层或掩模结构遮蔽的区域中。 氧注入部分被转换成深沟槽隔离结构，其与作为堆叠中的半导体部分的有源区的侧壁自对准。 将掺杂离子注入深沟槽隔离结构之间的底层半导体层的部分，以形成掺杂半导体背栅区。 在深沟槽隔离结构和堆叠之间形成浅沟槽隔离结构。

公开(公告)号：US20100203717A1

公开(公告)日：2010-08-12

申请号：US12698448

申请日：2010-02-02

申请人： Sivananda K. Kanakasabapathy ,  Veeraraghavan S. Basker ,  Balasubramanian S. Haran

发明人： Sivananda K. Kanakasabapathy ,  Veeraraghavan S. Basker ,  Balasubramanian S. Haran

IPC分类号： H01L21/28

CPC分类号： H01L29/4238 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

摘要： A multiple etch process for forming a gate in a semiconductor structure in which a cut area is first formed followed by the forming of the gate conductor lines.

摘要翻译： 在半导体结构中形成栅极的多次蚀刻工艺，其中首先形成切割区域，之后形成栅极导体线。

公开(公告)号：US08703553B2

公开(公告)日：2014-04-22

申请号：US13471955

申请日：2012-05-15

申请人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/8234 ,  H01L27/12

CPC分类号： H01L27/1288 ,  H01L21/823431 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1211 ,  H01L28/90

摘要： Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process.

摘要翻译： 用于电容器制造的方法包括在绝缘体上半导体衬底中掺杂半导体层的电容器区域; 部分地蚀刻半导体层以产生在掺杂半导体的剩余基底上包括掺杂半导体鳍片的第一端子层; 在所述第一端子层上形成介电层; 以及在finFET工艺中在所述介电层上形成第二端子层。

公开(公告)号：US08673738B2

公开(公告)日：2014-03-18

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08673708B2

公开(公告)日：2014-03-18

申请号：US13611044

申请日：2012-09-12

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。

公开(公告)号：US20140061582A1

公开(公告)日：2014-03-06

申请号：US13600324

申请日：2012-08-31

申请人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

IPC分类号： H01L29/06 ,  H01L21/20 ,  B82Y40/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

摘要： A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

摘要翻译： 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。

公开(公告)号：US08629008B2

公开(公告)日：2014-01-14

申请号：US13348018

申请日：2012-01-11

申请人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

发明人： Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth

IPC分类号： H01L21/02

CPC分类号： H01L29/0653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654

摘要： After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

摘要翻译： 在形成升高的源极和漏极区域之后，通过去除绝缘体上半导体（SOI）衬底中的浅沟槽隔离结构和掩埋绝缘体层的下面部分而形成的凹陷区域内淀积保形电介质材料衬垫。 随后沉积并平面化与保形介质材料衬垫的材料不同的介电材料，以形成平坦化的介电材料层。 平坦化的介电材料层对保形介电材料衬垫有选择性的凹陷，以形成填充凹陷区域的介电填充部分。 通过各向异性蚀刻去除保形电介质材料衬里的水平部分，而保形介质材料衬垫的剩余部分形成外栅间隔件。 沉积至少一个接触电介质层。 可以在接触通孔内形成与手柄基板电隔离的结构的接触。

公开(公告)号：US20130319613A1

公开(公告)日：2013-12-05

申请号：US13545456

申请日：2012-07-10

申请人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Veeraraghavan S. Basker ,  Huiming Bu ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Nicolas Loubet ,  Shom Ponoth ,  Stefan Schmitz ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L21/308

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/6681

摘要： A method for making dual-epi FinFETs is described. The method includes adding a first epitaxial material to an array of fins. The method also includes covering at least a first portion of the array of fins using a first masking material and removing the first epitaxial material from an uncovered portion of the array of fins. Adding a second epitaxial material to the fins in the uncovered portion of the array of fins is included in the method. The method also includes covering a second portion of the array of fins using a second masking material and performing a directional etch using the first masking material and the second masking material. Apparatus and computer program products are also described.

摘要翻译： 描述了制造双外延FinFET的方法。 该方法包括将第一外延材料添加到翅片阵列。 该方法还包括使用第一掩蔽材料覆盖翅片阵列的至少第一部分并且从翅片阵列的未覆盖部分移除第一外延材料。 在散热片阵列的未覆盖部分中的翅片上添加第二外延材料包括在该方法中。 该方法还包括使用第二掩模材料覆盖翅片阵列的第二部分，并使用第一掩模材料和第二掩模材料执行定向蚀刻。 还描述了装置和计算机程序产品。