公开(公告)号：US07098121B2

公开(公告)日：2006-08-29

申请号：US10367854

申请日：2003-02-19

申请人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

发明人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

IPC分类号： H01L21/22

CPC分类号： H01L21/3127 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/1292

摘要： An object is to provide a mask formation method, which can curtail a manufacturing cost.A method of forming a film of predetermined pattern on the front surface of a member to-be-processed is so constructed as to carry out the step (S178) of improving the adherence of a pattern material solution to the member to-be-processed, the step (S180) of filling up a pattern forming recess provided in a mask on the surface of the member to-be-processed with a pattern material solution, the step (S186) of improving the film quality of the pattern film to-be-formed by processing the pattern material solution, the step (S188) of removing the pattern material solution having adhered on the mask, the step (S190) of drying the pattern material solution, and the step (S196) of subjecting the pattern film to annealing processing.

摘要翻译： 目的在于提供掩模形成方法，可以减少制造成本。 在待处理构件的正面上形成预定图案的膜的方法被构造成执行改善图案材料溶液与要被加工的构件的粘附的步骤（S 178） 在图案材料溶液的待处理部件的表面上填充设置在掩模中的图案形成用凹部的工序（S180），提高图案的膜质量的工序（S188） 通过处理图案材料溶液形成的薄膜，去除已经粘附在掩模上的图案材料溶液的步骤（S 188），干燥图案材料溶液的步骤（S190）和步骤（S1996） ）对图案膜进行退火处理。

公开(公告)号：US07091546B2

公开(公告)日：2006-08-15

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L29/772

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US06907394B1

公开(公告)日：2005-06-14

申请号：US09570389

申请日：2000-05-12

申请人： Mitsuru Sato

发明人： Mitsuru Sato

IPC分类号： G01R31/28 ,  G06F9/45 ,  G06F17/50 ,  G06G7/62 ,  H01L21/82

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： A device for simulating circuits is provided with an identifying system and a verifying system. The identifying system identifies a pair of wires in which two signals operate simultaneously within an appointed period and a pair of wires in which two signals do not operate almost simultaneously within the appointed period. The verifying system verifies actions of a circuit to be analyzed, under an assumption that the coupling capacitor between the pair of wires in which it is judged by the identifying system that two signals do not simultaneously operate within the appointed period is a ground capacitor.

摘要翻译： 用于模拟电路的装置设置有识别系统和验证系统。 识别系统识别一条电线，其中两个信号在指定时间段内同时操作，并且一对电线，其中两个信号在指定时段内几乎不同时操作。 验证系统验证要分析的电路的动作，假设由识别系统判断两条信号在指定时段内不同时工作的一对导线之间的耦合电容器是接地电容器。

公开(公告)号：US20050095801A1

公开(公告)日：2005-05-05

申请号：US10947388

申请日：2004-09-23

申请人： Mitsuru Sato ,  Hirofumi Inoue

发明人： Mitsuru Sato ,  Hirofumi Inoue

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor comprises a semiconductor substrate, a trench provided in the semiconductor substrate, a first doped polysilicon filled in the trench at a lower end of the trench via a first dielectric film, and a second doped polysilicon filled in the trench at an upper end of the trench via a second dielectric film, the second doped polysilicon being contiguously disposed to the first doped polycrystal silicon, wherein the second dielectric film consists of an oxide film using radicals.

摘要翻译： 沟槽电容器包括半导体衬底，设置在半导体衬底中的沟槽，经由第一电介质膜填充在沟槽的下端处的沟槽中的第一掺杂多晶硅，以及在上端填充在沟槽中的第二掺杂多晶硅 的第二电介质膜，所述第二掺杂多晶硅连续地设置在所述第一掺杂多晶硅上，其中所述第二电介质膜由使用自由基的氧化膜组成。

公开(公告)号：US06657877B2

公开(公告)日：2003-12-02

申请号：US09966769

申请日：2001-09-28

申请人： Masato Kashima ,  Mitsuru Sato ,  Eiji Kuroda ,  Hironobu Shiroyama

发明人： Masato Kashima ,  Mitsuru Sato ,  Eiji Kuroda ,  Hironobu Shiroyama

IPC分类号： H02M7217

CPC分类号： H02M7/217 ,  H02M3/156

摘要： A power supply circuit improves the power factor when the load is light, and incorporates a starting circuit for reacting quickly to the changes in the output from the power supply circuit and a short-circuit detecting means for detecting the short-circuit of the feedback signal. The apparatus includes: an error amplifier; a comparator that monitors the output from the error amplifier and generates an offset regulating current ISO; a multiplier; a sensing current comparator that compares the output signal from the multiplier and the AC line current and generates a reset signal; a timer that directly monitors the inputted zero-cross signal; and a comparator for short-circuit detection, that facilitates reducing the exterior parts and components.

公开(公告)号：US06540219B1

公开(公告)日：2003-04-01

申请号：US09646282

申请日：2000-10-12

申请人： Akira Naruse ,  Kouichi Kumon ,  Mitsuru Sato

发明人： Akira Naruse ,  Kouichi Kumon ,  Mitsuru Sato

IPC分类号： B65H106

CPC分类号： B65H3/5238 ,  B65H3/063 ,  B65H3/54 ,  B65H2403/42 ,  B65H2403/481 ,  B65H2513/41 ,  B65H2513/51 ,  B65H2220/02 ,  B65H2220/01

摘要： A paper feed apparatus having a pickup mechanism to pick up a plurality of paper sheets stacked on a chute one by one from the bottom and carrying the paper sheets to a predetermined standby position, comprises a gate 2 disposed facing a pickup roller 1 almost vertically with respect to the direction of paper feed to form a predetermined clearance, a paper-sheet separating pad 3 disposed in sliding contact with the pickup roller 1 to pick up the paper placed on the standby position one by one, and a pickup arm 4 that can be driven to be moved upward when setting paper sheets and downward when feeding paper sheets to push from above the paper sheets stacked on a chute 13 near a paper-sheet feed port. The pickup arm 4,when brought into free state as the planetary gear 5 disengages from the drive power transmission system, pushes paper sheets with a pushing force that increases with increases in the number of paper sheets stacked on the chute 13.

摘要翻译： 一种具有拾取机构的进纸装置，用于从底部一个接一个地从底部拾取多个纸张，并将纸张运送到预定的待机位置，包括：几乎垂直地面向拾取辊1设置的门2， 相对于进纸方向形成预定的间隙，设置成与拾取辊1滑动接触的纸张分离垫3一个接一个地拾起放置在备用位置上的纸张;以及拾取臂4，其可以 当纸张从纸张上方堆放在靠近纸张进纸口的滑槽13上方时，将纸张向下移动以向上移动。 当行星齿轮5与驱动动力传动系统脱离接合时，拾取臂4随着随着在滑槽13上堆叠的纸张数量的增加而增加的推力推动纸张。

公开(公告)号：US06526480B1

公开(公告)日：2003-02-25

申请号：US09646704

申请日：2000-09-21

申请人： Akira Naruse ,  Kouichi Kumon ,  Mitsuru Sato

发明人： Akira Naruse ,  Kouichi Kumon ,  Mitsuru Sato

IPC分类号： G06F1200

CPC分类号： G06F9/3834 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0815 ,  G06F12/0831

摘要： The invention relates to cache apparatuses and a control method for managing cache memories in a multiprocessor system. A cache controller holds data which has to be invalidated for a cache coherence as data in a status where the validity is unknown, causes a cache hit in response to a reading request from a processor, provides the data as speculation data, and allows the processor to speculatively process the data. Therefore, since the data which has to be obtained from another cache or a main storage due to the invalidation is held in an Unknown status, a cache hit occurs. Thus, a data waiting time of the processor can be shortened.

摘要翻译： 本发明涉及高速缓存设备和用于在多处理器系统中管理高速缓存存储器的控制方法。 高速缓存控制器将对于高速缓存一致性必须被无效的数据保存为有效性未知状态的数据，导致响应于来自处理器的读取请求的高速缓存命中，将数据提供为推测数据，并允许处理器 推测处理数据。 因此，由于由于无效而必须从另一高速缓存或主存储器获得的数据保持在未知状态，所以发生高速缓存命中。 因此，可以缩短处理器的数据等待时间。

公开(公告)号：US06282160B1

公开(公告)日：2001-08-28

申请号：US09271316

申请日：1999-03-18

申请人： Kiyoshi Tateishi ,  Mitsuru Sato

发明人： Kiyoshi Tateishi ,  Mitsuru Sato

IPC分类号： G11B700

CPC分类号： G11B19/247 ,  G11B7/0037 ,  G11B7/00745 ,  G11B19/12

摘要： Disclosed is a disc player for obtaining a read signal from an optical disc having sectors including land and groove tracks and ID regions, preformatted at given angular spatial intervals, which demarcate the sectors and are segmented, in the track extending direction, into two regions, each segmented region including a plural number of recording regions and non-recording regions, which are alternately and radially arrayed while being radially shifted by approximately half a track pitch from the tracks of the sectors adjacent to the segmented regions, each recording region containing record position information recorded therein having predetermined time durations. The disc player comprises: optical read means for projecting a light beam onto the optical disc and receiving a light beam reflected from a recording surface of the optical disc; first and second signal generating means for generating first and second signals which are dependent on the record position information recorded in the recording regions of the first and second segmented regions by use of a signal output from the optical read means; and ID region detecting means for outputting a detecting signal indicating that the ID region is detected when the first and second signals are both present.

摘要翻译： 公开了一种光盘播放器，用于从具有扇区的光盘获得读取信号，所述扇区包括具有纹间和纹道轨迹和ID区域的扇区，以特定的角度空间间隔预先格式化，将扇区划分成轨道延伸方向并分段成两个区域， 每个分段区域包括多个记录区域和非记录区域，它们从与分段区域相邻的扇区的轨道径向偏移约半个轨道间距，每个记录区域包含记录位置 其中记录的信息具有预定的持续时间。 光盘播放器包括：光学读取装置，用于将光束投射到光盘上并接收从光盘的记录表面反射的光束; 第一和第二信号产生装置，用于通过使用从光学读取装置输出的信号产生依赖于记录在第一和第二分割区域的记录区域中的记录位置信息的第一和第二信号; 以及ID区域检测装置，用于当第一和第二信号都存在时，输出指示检测到ID区域的检测信号。

公开(公告)号：US06281571B1

公开(公告)日：2001-08-28

申请号：US09537803

申请日：2000-03-24

申请人： Akira Takashima ,  Fumihiko Ando ,  Mitsuru Sato ,  Takashi Suzuki ,  Yoshikazu Kumagaya ,  Kazunari Kosakai

发明人： Akira Takashima ,  Fumihiko Ando ,  Mitsuru Sato ,  Takashi Suzuki ,  Yoshikazu Kumagaya ,  Kazunari Kosakai

IPC分类号： H01L2304

CPC分类号： H01L24/83 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/85444 ,  H01L2224/8547 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0394 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/05442 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： External connection electrodes can be positively mounted on a substrate when the pitch between the external connection electrodes is reduced and the diameter of each through hole formed in the substrate is reduced. A semiconductor chip is mounted on a first surface of a tape substrate. Electrode films are formed on the first surface of the tape substrate, each of the electrode films electrically connected to the semiconductor chip. External connection electrodes are provided on a second surface of the tape substrate, each of the external connection electrodes connected to a respective one of the electrode films via a through hole formed in the tape substrate. The external connection electrodes are formed on the electrode films by plating. A diameter S1 of a portion of each of the external connection electrodes protruding from the second surface of the tape substrate and a diameter S2 of the through hole satisfy a relationship S1≦S2.

摘要翻译： 当外部连接电极之间的间距减小并且形成在基板中的每个通孔的直径减小时，可以将外部连接电极牢固地安装在基板上。 半导体芯片安装在带基板的第一表面上。 在带基板的第一表面上形成电极膜，每个电极膜与半导体芯片电连接。 外部连接电极设置在带基板的第二表面上，每个外部连接电极通过形成在带基板中的通孔连接到相应的一个电极膜。 外部连接电极通过电镀形成在电极膜上。 每个外部连接电极的从带基板的第二表面突出的部分的直径S1和通孔的直径S2满足关系S1 <= S2。

公开(公告)号：US06232795B1

公开(公告)日：2001-05-15

申请号：US09657190

申请日：2000-09-07

申请人： Hiroyuki Takahashi ,  Mitsuru Sato

发明人： Hiroyuki Takahashi ,  Mitsuru Sato

IPC分类号： H03K19094

CPC分类号： H03K19/09448

摘要： A logic circuit performs a predetermined logic operation by supplying charge to an external load or pulling out charge therefrom according to a combination of the states of a plurality of externally inputted binary signals. The logic circuit includes a first transistor for supplying charge through an output terminal to the external load and a second transistor for pulling out the charge from the load through the output terminal. One of the first and second transistors is constituted by a MOS field-effect transistor having a drain connected to the output terminal. The MOS field-effect transistor has a source receiving an inverse signal inverse to a signal combined for logic operation with an input signal inputted to a gate of the MOS field-effect transistor. The number of the series transistors is reduced, resulting in an increase of the current capacity and in a reduction of the layout area. Adjacent ones of the logic circuits have a common source diffusion layer so that the load capacitance with respect to the inverse signal can be significantly reduced, thus enabling the high speed operation.

摘要翻译： 逻辑电路通过根据多个外部输入的二进制信号的状态的组合向外部负载提供电荷或从其中提取电荷来执行预定的逻辑运算。 逻辑电路包括用于通过输出端子向外部负载提供电荷的第一晶体管和用于通过输出端从负载中拉出电荷的第二晶体管。 第一和第二晶体管中的一个由具有连接到输出端子的漏极的MOS场效应晶体管构成。 MOS场效应晶体管具有与输入到MOS场效应晶体管的栅极的输入信号相反接收与组合用于逻辑运算的信号的反相信号的源。 串联晶体管的数量减少，导致电流容量的增加和布局区域的减少。 相邻的逻辑电路具有公共的源极扩散层，从而可以显着地减少相对于反向信号的负载电容，从而实现高速运行。