公开(公告)号：US06456521B1

公开(公告)日：2002-09-24

申请号：US09814418

申请日：2001-03-21

申请人： Louis L. Hsu ,  Rajiv V. Joshi

发明人： Louis L. Hsu ,  Rajiv V. Joshi

IPC分类号： G11C1124

CPC分类号： G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

摘要： A hierarchical bitline DRAM architecture system is disclosed having a DRAM array which includes master and local bitlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting the chip's performance, including high random access speed and short cycle time. The DRAM array is designed to be noise-free and to prevent data from being lost during read/write operations. The DRAM array includes a folded-bitline differential sensing scheme and high array efficiency. The DRAM array has a minimum amount of sense amplifiers as compared to conventional DRAMs to save chip area and conserve power. The DRAM array is capable of storing data in both the single-cell and twin-cell array format and is interchangeable between single-cell and twin-cell array operation. The hierarchical bitline DRAM architecture system is extended to provide a hierarchical bitline and wordline DRAM architecture system having a DRAM array which includes master and local bitlines and master and local wordlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting the chip's performance, including high random access speed and short cycle time.

摘要翻译： 公开了一种具有DRAM阵列的分级位线DRAM架构系统，其包括用于实现具有低功耗，高密度和小尺寸的DRAM芯片的主和局部位线，而不影响芯片的性能，包括高随机存取速度和短周期时间 。 DRAM阵列被设计为无噪声，并防止在读/写操作期间数据丢失。 DRAM阵列包括折叠位线差分感测方案和高阵列效率。 与常规DRAM相比，DRAM阵列具有最小量的读出放大器，以节省芯片面积并节省功率。 DRAM阵列能够以单电池和双电池阵列格式存储数据，并可在单电池和双电池阵列操作之间互换。 分级位线DRAM架构系统被扩展以提供具有DRAM阵列的分级位线和字线DRAM架构系统，其包括主和局部位线以及用于实现具有低功耗，高密度和小尺寸的DRAM芯片的主和本地字线 而不影响芯片的性能，包括高随机存取速度和较短的周期时间。

公开(公告)号：US06445638B1

公开(公告)日：2002-09-03

申请号：US09665016

申请日：2000-09-19

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Radens Carl

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Radens Carl

IPC分类号： G11C1300

CPC分类号： G11C11/40603 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4097

摘要： A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which also prioritizes two simultaneous access requests slated for the DRAM cell of a data array. If the two access requests are write-read or read-write, then the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access or the read and write access requests by accessing the corresponding DRAM cell through the first port or second port, respectively, to write the data while simultaneously writing the data through to an output bus.

摘要翻译： 提出了一种双端口折叠位线DRAM架构系统，其优先考虑在执行至少一个访问请求之前为数据阵列的DRAM单元预定的两个同时访问请求，以防止影响数据的完整性同时抑制由于 到字线到位线耦合，位线到位线耦合和位线到衬底耦合。 如果两个访问请求是写入读取的，则系统将两个访问请求的优先级彼此相等。 然后，该系统通过访问通过第一端口的对应的DRAM单元同时执行写入和读取访问，以在同时将数据写入到等效于读取访问的输出总线的同时写入数据。 在本发明的另一个实施例中，提出了一种双端口共享地址总线DRAM架构系统，其还优先考虑为数据阵列的DRAM单元设置的两个同时访问请求。 如果两个访问请求是写入或读写，则系统将两个访问请求的优先顺序相互相等。 然后，系统通过分别通过第一端口或第二端口访问相应的DRAM单元来同时执行写入和读取访问或读取和写入访问请求，以在同时将数据写入输出总线的同时写入数据。

公开(公告)号：US06396324B1

公开(公告)日：2002-05-28

申请号：US09566311

申请日：2000-05-08

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Richard M. Parent ,  Matthew R. Wordeman

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Richard M. Parent ,  Matthew R. Wordeman

IPC分类号： G06F104

CPC分类号： G11C7/225 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222

摘要： A clock system is provided capable of using an external system clock for driving at least one charge circuit of a semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system, in one embodiment, includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.

摘要翻译： 提供一种时钟系统，其能够使用外部系统时钟来驱动用于恢复和刷新存储器单元的数据阵列的半导体存储器单元的至少一个充电电路。 在一个实施例中，时钟系统包括多个控制电路，每个控制电路具有时钟选择电路，该时钟选择电路具有作为输入的外部系统时钟，用于产生内部系统时钟的内部时钟发生器电路和多路复用器。 多路复用器具有时钟选择电路的输出，即外部系统时钟和内部时钟发生器电路的输出，即内部系统时钟的输入。 根据由中央处理单元发送到时钟选择电路的至少一个控制信号，多路复用器将外部系统时钟或内部系统时钟输出到至少一个充电电路。

公开(公告)号：US5585673A

公开(公告)日：1996-12-17

申请号：US346208

申请日：1994-11-22

申请人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

发明人： Rajiv V. Joshi ,  Jerome J. Cuomo ,  Hormazdyar M. Dalal ,  Louis L. Hsu

IPC分类号： H01L21/28 ,  H01L21/312 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L29/43

CPC分类号： H01L21/76843 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/49866 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S148/015 ,  Y10S257/915 ,  Y10S438/959

摘要： Capping a low resistivity metal conductor line or via with a refractory metal allows for effectively using chemical-mechanical polishing techniques because the hard, reduced wear, properties of the refractory metal do not scratch, corrode, or smear during chemical-mechanical polishing. Superior conductive lines and vias are created using a combination of both physical vapor deposition (e.g., evaporation or collimated sputtering) of a low resistivity metal or alloy followed by chemical vapor deposition (CVD) of a refractory metal and subsequent planarization. Altering a ratio of SiH.sub.4 to WF.sub.6 during application of the refractory metal cap by CVD allows for controlled incorporation of silicon into the tungsten capping layer. Collimated sputtering allows for creating a refractory metal liner in an opening in a dielectric which is suitable as a diffusion barrier to copper based metalizations as well as CVD tungsten. Ideally, for faster diffusing metals like copper, liners are created by a two step collimated sputtering process wherein a first layer is deposited under relatively low vacuum pressure where directional deposition dominates (e.g., below 1 mTorr) and a second layer is deposited under relatively high vacuum pressure where scattering deposition dominates (e.g., above 1 mTorr). For refractory metals like CVD tungsten, the liner can be created in one step using collimated sputtering at higher vacuum pressures.

公开(公告)号：US5382832A

公开(公告)日：1995-01-17

申请号：US131344

申请日：1993-10-04

申请人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

发明人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

IPC分类号： H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/48 ,  H01L27/01

CPC分类号： H01L25/50 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/977

摘要： A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

摘要翻译： 公开了一种适于在其上形成半导体器件的晶片结构，并且具有用于根据预定互连图案互连所需半导体器件的掩埋互连结构及其制造方法。 晶片结构包括具有适于形成期望的半导体器件的第一厚度的初级衬底。 主衬底还包括：a）根据预定互连图案形成在初级衬底的底表面上的第二厚度的导电互连衬垫，b）形成在第一衬底的底表面上的第三厚度的第一隔离衬垫 导电互连焊盘，以及c）形成在与主基板相对的互连焊盘的表面上的第四厚度的互连焊盘盖，其中互连焊盘帽包括适于晶片接合的材料，并且其中第二厚度 厚度和第四厚度等于第三厚度。 该结构还包括其上结合有互连衬垫帽和主晶片的第一隔离垫的氧化物层的二次衬底。

公开(公告)号：US20110256720A1

公开(公告)日：2011-10-20

申请号：US13169248

申请日：2011-06-27

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  David W. Kruger

IPC分类号： H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76834 ,  H01L23/573 ,  H01L27/02 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer.

摘要翻译： 提供了反逆向工程技术。 一方面，提供了一种在绝缘层中形成至少一个特征的方法。 该方法包括以下步骤。 离子选择性地植入绝缘层中，以在绝缘层内形成至少一个注入区域，所述注入离子被配置为改变通过植入区域内的绝缘层的蚀刻速率。 蚀刻绝缘层，同时在植入区域内和植入区域外部形成至少一个空隙，其中通过绝缘层在植入区域内的蚀刻速率与通过绝缘体的蚀刻速率不同 在植入区域外侧。 空隙填充有至少一种导体材料以在绝缘层中形成特征。

公开(公告)号：US07113006B2

公开(公告)日：2006-09-26

申请号：US11065840

申请日：2005-02-25

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman

IPC分类号： H03K5/22 ,  H03K5/153 ,  H01G23/00

CPC分类号： H02M3/07

摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.

摘要翻译： 具有改进的可靠性的电容器电路包括至少第一和第二电容器，第一电容器的第一端子连接到提供第一电压的第一源极，第二电容器的第一端子连接到提供第二电压的第二源极，第一电容器 电压大于第二电压。 电容器还包括电压比较器，具有用于接收表示第一电压的电压的第一输入端，用于接收由第三源极提供的第三电压的第二输入端和用于产生控制信号的输出端。 控制信号是代表第一电压和第三电压的电压之差的函数。 开关连接到第一和第二电容器的第二端子。 响应于控制信号，开关选择性地可操作于至少第一模式和第二模式之一中，其中在第一模式中，开关可操作以并联连接第一和第二电容器，并且在第二模式中， 开关可操作以串联连接第一和第二电容器。 第一模式表示代表第一电压的电压小于或等于第三电压，第二模式表示代表第一电压的电压大于第三电压。

公开(公告)号：US07093171B2

公开(公告)日：2006-08-15

申请号：US10115348

申请日：2002-04-03

申请人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

发明人： Louis L. Hsu ,  Gregory J. Fredeman ,  Rajiv V. Joshi ,  Toshiaki Kirihata

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

摘要翻译： 提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。 行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

公开(公告)号：US06992917B2

公开(公告)日：2006-01-31

申请号：US10736414

申请日：2003-12-15

申请人： William R. Dachtera ,  Louis L. Hsu ,  Rajiv V. Joshi

发明人： William R. Dachtera ,  Louis L. Hsu ,  Rajiv V. Joshi

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： H03K19/00384 ,  H01L27/1203 ,  H01L29/78612

摘要： An integrated circuit (IC), random access memory on an IC and method of neutralizing device floating body effects. A floating body effect monitor monitors circuit/array activity and selectively provides an indication of floating body effect manifestation from inactivity, including the lapse of time since the most recent activity or memory access. A pulse generator generates a neutralization pulse in response to an indication of inactivity. A neutralization pulse distribution circuit passes the neutralization pulse to blocks in the circuit path or to array cells.

摘要翻译： 集成电路（IC），IC上的随机存取存储器以及中和器件浮体效应的方法。 浮体效应监视器监视电路/阵列活动，并且选择性地提供来自不活动的浮体影响表现的指示，包括自最近的活动或存储器访问以来的时间流逝。 脉冲发生器响应于不活动的指示产生中和脉冲。 中和脉冲分配电路将中和脉冲传递到电路路径中的块或阵列单元。

公开(公告)号：US06906354B2

公开(公告)日：2005-06-14

申请号：US09880223

申请日：2001-06-13

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi

IPC分类号： G11C11/39 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/12 ,  H01L29/32 ,  H01L29/423

CPC分类号： G11C11/39 ,  H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1112 ,  H01L27/1203

摘要： A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual devices. Each T-RAM cell is planar and has a buried vertical thyristor and a horizontally stacked pseudo-TFT transfer gate. The buried vertical thyristor is located beneath the horizontally stacked pseudo-TFT transfer gate. A method is also presented for fabricating the T-RAM array having the buried vertical thyristors, the horizontally stacked pseudo-TFT transfer gates and the planar cell structure.

摘要翻译： 呈现具有多个T-RAM单元的T-RAM阵列，其中每个T-RAM单元具有双器件。 每个T-RAM单元是平面的并且具有埋入的垂直晶闸管和水平堆叠的伪TFT传输门。 埋置的垂直晶闸管位于水平堆叠的伪TFT传输门的下方。 还提出了一种用于制造具有埋入垂直晶闸管，水平堆叠的伪TFT传输门和平面单元结构的T-RAM阵列的方法。