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    Interrupt emulation on network devices
    41.
    发明授权
    Interrupt emulation on network devices 有权

    公开(公告)号：US12174765B2

    公开(公告)日：2024-12-24

    申请号：US17707555

    申请日：2022-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Daniel Marcovitch ,  Liran Liss ,  Rabia Loulou ,  Aviad Yehezkel

    IPC: G06F13/24 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

    Abstract: Methods, systems, and devices for message signaled interrupt (MSI-X) tunneling on a host device exposed by a bridge connection are described. A device may receive data and a first interrupt signal from a remote destination over a network protocol. The device may receive the data and/or the first interrupt signal over the bridge connection, via a tunneled communication from the remote destination. The device may generate a second interrupt signal based on the first interrupt signal and a local interrupt configuration provided by a system bus driver of the device. The device may inject the data and the second interrupt signal over the system bus. Injecting the data and injecting the second interrupt signal may include ensuring the data is made available to the system bus driver, prior to the interrupt handler receiving the second interrupt signal.

    Network device with datagram transport layer security
    42.
    发明申请
    Network device with datagram transport layer security 有权

    公开(公告)号：US20240406212A1

    公开(公告)日：2024-12-05

    申请号：US18595475

    申请日：2024-03-05

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Miriam Menes ,  Liran Liss

    IPC: H04L9/40 ,  H04L9/08

    Abstract: In one embodiment, a local networking device includes a host interface to receive packets from a local host device, packet processing hardware to receive cryptographic material offloaded from the local host device over the host interface, perform cryptographic operations on the packets based on the cryptographic material, generate datagram transport layer security (DTLS) headers including respective DTLS sequence numbers in hardware, and encapsulate the packets with the DTLS headers in hardware, and a network interface to send the packets with the DTLS headers to a remote networking device over a packet data network.

    Zero-copy processing
    47.
    发明授权
    Zero-copy processing 有权

    公开(公告)号：US11757796B2

    公开(公告)日：2023-09-12

    申请号：US17488362

    申请日：2021-09-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Haggai Eran ,  Liran Liss ,  Yuval Shpigelman ,  Idan Burstein

    IPC: H04L61/00 ,  H04L49/00 ,  H04L12/40 ,  H04L49/90

    CPC classification number: H04L49/3072 ,  H04L12/40071 ,  H04L49/9042

    Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST
    50.
    发明公开
    SYSTEM WHICH PROVIDES PLURAL PROCESSES IN A HOST WITH ASYNCHRONOUS ACCESS TO PLURAL PORTIONS OF THE MEMORY OF ANOTHER HOST 审中-公开

    公开(公告)号：US20230176769A1

    公开(公告)日：2023-06-08

    申请号：US17543334

    申请日：2021-12-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gal Shalom ,  Adi Horowitz ,  Omri Kahalon ,  Liran Liss ,  Aviad Yehezkel ,  Rabie Loulou

    IPC: G06F3/06 ,  G06F9/54

    CPC classification number: G06F3/0655 ,  G06F9/544 ,  G06F3/061 ,  G06F3/0673

    Abstract: API in conjunction with a bridge chip and first and second hosts having first and second memories respectively. The bridge chip connects the memories. The API comprises key identifier registration functionality to register a key identifier for each of plural computer processes performed by the first host, thereby to define plural key identifiers; and/or access control functionality to provide at least computer process P1 performed by the first host with access, typically via the bridge chip, to at least local memory buffer M2 residing in the second memory, typically after the access control functionality first validates that process P1 has a key identifier which has been registered, e.g., via the key identifier registration functionality. Typically, the access control functionality also prevents at least computer process P2, performed by the first host, which has not registered a key identifier, from accessing local memory buffer M2, e.g., via the bridge chip.

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