公开(公告)号：US20240072024A1

公开(公告)日：2024-02-29

申请号：US17897156

申请日：2022-08-27

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Seng Kim Ye ,  Chin Hui Chong

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L25/162 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/35121

Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.

公开(公告)号：US20240047423A1

公开(公告)日：2024-02-08

申请号：US17879660

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng ,  Chin Hui Chong

IPC: H01L25/065 ,  H01L21/304

CPC classification number: H01L25/0657 ,  H01L21/3043 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L2924/10158 ,  H01L24/48

Abstract: A semiconductor device assembly is provided. The assembly includes an outer semiconductor device which has an active surface and a back surface. The back surface includes a cut that extends to a depth between the active surface and the back surface, and uncut regions on opposing sides of the cut. The assembly further includes an inner semiconductor device disposed within the cut of the outer semiconductor device.

公开(公告)号：US20230378043A1

公开(公告)日：2023-11-23

申请号：US17750140

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Chin Hui Chong ,  Seng Kim Ye ,  Kelvin Tan Aik Boo ,  Hong Wan Ng

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4846

Abstract: Semiconductor devices with three-dimensional trace matching features, and related systems and methods, are disclosed herein. In some embodiments, an exemplary semiconductor device includes at least one semiconductor die and a redistribution layer disposed over the at least one semiconductor die and extending across a longitudinal plane. The redistribution layer includes first and second traces each electrically coupled to the at least one semiconductor die. The first trace is disposed in a first travel path included in a first effective path length. The second trace is disposed in a second travel path different from the first travel path. The second the second travel path includes at least one segment at a non-right, non-zero angle such that the at least one segment is neither parallel nor perpendicular to the longitudinal plane. Further, the second travel path is included in a second effective path length equal to the first path length.

公开(公告)号：US11824044B2

公开(公告)日：2023-11-21

申请号：US17409427

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/8385 ,  H01L2224/83191 ,  H01L2224/8592 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2924/0665

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.

公开(公告)号：US11723150B2

公开(公告)日：2023-08-08

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/642 ,  H01L25/0657 ,  H05K1/181 ,  H01L23/49816 ,  H05K2201/10015 ,  H05K2201/10159

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US20230207488A1

公开(公告)日：2023-06-29

申请号：US17976409

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong ,  Wei Yu ,  Ling Pan ,  Lin Bu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/50 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32245

Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

公开(公告)号：US11527459B2

公开(公告)日：2022-12-13

申请号：US17243466

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Chin Hui Chong ,  Hem P. Takiar ,  Seng Kim Ye ,  Kelvin Tan Aik Boo

IPC: H01L29/76 ,  H01L29/00 ,  H01L23/48 ,  H01L27/08 ,  H01L49/02 ,  H01L23/498

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.

公开(公告)号：US20220181307A1

公开(公告)日：2022-06-09

申请号：US17682948

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tam Aik Boo ,  Chin-Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

公开(公告)号：US20220078915A1

公开(公告)日：2022-03-10

申请号：US17012817

申请日：2020-09-04

Applicant: Micron Technology, Inc.

Inventor： Kelvin Tan Aik Boo ,  Chin Hui Chong ,  Seng Kim Ye ,  Hong Wan Ng ,  Hem P. Takiar

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

公开(公告)号：US11101244B2

公开(公告)日：2021-08-24

申请号：US16876520

申请日：2020-05-18

Applicant: Micron Technology, Inc.

Inventor： Seng Kim Ye ,  Hong Wan Ng

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/31

Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.