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公开(公告)号：US6019665A
公开(公告)日：2000-02-01
申请号：US070587
申请日：1998-04-30
申请人： Michael G. Lee , Solomon I. Beilin
发明人： Michael G. Lee , Solomon I. Beilin
摘要： A weir with locks is used to encompass a platen used for chemical-mechanical polishing. The weir retains slurry that would otherwise be flung from a rotating platen because of centrifugal force. However, the locks permit some slurry to leave the platen, which enables the polishing process to include desirable flows of fresh slurry through the polishing pad to replenish polishing components and to flush out deleterious waste products. Additionally, the effective orifice size of the locks may be made a function of platen rotation rate. Polishing processes are possible in which the depth of the polishing slurry on the platen is a function of platen rotation rate.
摘要翻译： 带锁的堰被用于包括用于化学机械抛光的压板。 堰保留由于离心力而将由旋转台板抛出的浆料。 然而，这些锁允许一些浆料离开压板，这使得抛光过程能够包括所需的新鲜浆料流经抛光垫以补充抛光组分并冲洗出有害废物。 此外，锁的有效孔尺寸可以作为压板旋转速率的函数。 抛光过程是可能的，其中在台板上的抛光浆料的深度是压板旋转速率的函数。
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42.发明授权
公开(公告)号：US5916453A
公开(公告)日：1999-06-29
申请号：US717266
申请日：1996-09-20
申请人： Solomon I. Beilin , Michael G. Lee , William T. Chou , Larry Louis Moresco , Wen-chou Vincent Wang
发明人： Solomon I. Beilin , Michael G. Lee , William T. Chou , Larry Louis Moresco , Wen-chou Vincent Wang
IPC分类号： H01L21/3105 , H01L21/321 , H05K3/24 , H05K3/46 , C25F3/16
CPC分类号： H01L21/31053 , H05K3/4647 , H05K2203/025 , H05K2203/0733 , H05K3/243
摘要： Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.
摘要翻译： 公开了在基板和晶片的表面上形成的结构的平面化方法。 所述方法在所述表面和所述结构或所述结构的形成位置上形成平坦化层，使得所述层的顶表面在所述结构的位置之间具有低区域，并且使得所述低区域基本上位于所述结构 在低于结构顶部的平面内。 然后在平坦化层的低区域上形成抛光停止层，抛光停止层比平坦化层更能抵抗抛光，并且优选地，结构。 然后将所得表面抛光。 抛光可以通过例如标准机械抛光和化学机械抛光来实现。
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公开(公告)号：US5509349A
公开(公告)日：1996-04-23
申请号：US47967
申请日：1993-04-15
申请人： Kyle T. Anderson , Duke W. Goss , Michael G. Lee
发明人： Kyle T. Anderson , Duke W. Goss , Michael G. Lee
CPC分类号： A47J31/36 , A47J31/42 , A47J31/4485 , A47J31/52 , Y10S261/16 , Y10S261/76 , Y10T137/87595 , Y10T137/87627
摘要： A fully automated cappuccino, latte, and espresso brewing machine which includes a refrigerated milk supply from which milk is drawn by a steam driven venturi apparatus. The venturi subcombination includes independently electrically operated valving for the driving steam, for drawing milk from its supply, and for drawing air, as desired, for foaming the milk in a vortex mixer coupled to the output of the venturi. The valving may be sequential so that with each cycle of use of the apparatus, it is hygienically steam cleaned of all milk residue.
摘要翻译： 一种完全自动化的卡布奇咖咖啡，拿铁咖啡和浓缩咖啡冲泡机，其包括冷藏牛奶供应，牛奶由蒸汽驱动的文丘里装置从中抽出。 文丘里亚组合包括用于驱动蒸汽的独立电动阀门，用于从其供应源抽取牛奶，并且根据需要抽吸空气，用于在连接到文氏管的输出端的涡流混合器中使牛奶发泡。 阀门可以是顺序的，使得在设备的每个循环使用时，对所有乳渣进行卫生地蒸汽清洁。
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公开(公告)号：US5454161A
公开(公告)日：1995-10-03
申请号：US54899
申请日：1993-04-29
CPC分类号： H01L21/486 , H01L23/49827 , H01L2224/16 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , Y10T29/49124 , Y10T29/49144 , Y10T29/49165
摘要： A high density through-hole interconnect with high aspect ratio vias is formed by sequentially forming layers of dielectric material on a previous dielectric layer. After each layer is formed, a plurality of through holes are etched through each layer and filled or metalized with an electrically conductive material having a coefficient of thermal expansion matching that of the dielectric layers and the integrated circuit that it will connect with. Preferably, the process of forming dielectric layers, forming through holes, and metalizing the through holes is repeated until the metalized through holes have an aspect ratio in the range of from 6 to 10. A support structure is constructed to interconnect with and support the metalized vias while the dielectric material is removed. A second dielectric material having the desired mechanical and electrical properties is poured into the support structure to fill the space between the metalized vias and allowed to solidify. The support structure is removed and the through-hole interconnector, comprising the metalized vias and the second dielectric material, is lapped and polished to predetermined manufacturing dimensions and tolerances.
摘要翻译： 具有高纵横比通孔的高密度通孔互连通过在先前的介电层上依次形成电介质材料层来形成。 在形成每一层之后，通过每个层蚀刻多个通孔，并用与其将连接的电介质层和集成电路的热膨胀系数匹配的导热材料填充或金属化。 优选地，重复形成电介质层，形成通孔和使通孔金属化的工艺，直到金属化通孔具有在6至10范围内的纵横比。支撑结构被构造成与金属化的 电介质材料被去除时的通孔。 将具有期望的机械和电学性能的第二介电材料倒入支撑结构中以填充金属化通孔之间的空间并使其固化。 移除支撑结构，并且将包括金属化通孔和第二介电材料的通孔互连器重叠并抛光至预定的制造尺寸和公差。
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公开(公告)号：US5323520A
公开(公告)日：1994-06-28
申请号：US054910
申请日：1993-04-29
CPC分类号： H01G4/232 , H01G4/306 , H05K1/162 , H01L2224/16145 , H01L2224/16225 , H01L2924/1305 , H05K1/112 , H05K2201/0317 , H05K2201/09309 , H05K2203/0315 , Y10T29/435 , Y10T29/49165
摘要： A thin-film bypass capacitor is fabricated by forming a plurality of through holes through the thickness of a nonconductive base substrate and filling the through holes with a conductive material to form ground vias and power vias. A sequence of back side metalization layers are applied to the back side surface of the base substrate. A sequence of bottom contact layers are applied to the front side surface of the base substrate. A bottom contact power terminal is formed and a bottom contact metalization layer is applied to the surface of the bottom contact layers. A portion of the metalization layer is removed and an insulating layer is formed on the surface of the bottom contact metalization layer. A ground metalization feedthrough and a power metalization feedthrough are formed at the surface of the insulating layer. A sequence of top contact layers are applied to the surface of the insulating layer and a front side ground terminal and front side power terminal are formed. A back side ground terminal and a back side power terminal are formed at the back side of the base substrate.
摘要翻译： 通过形成穿过非导电基底基板的厚度的多个通孔并用导电材料填充通孔来形成薄膜旁路电容器，以形成接地通孔和电源通孔。 将背面金属化层序列施加到基底基板的背面。 底部接触层序列被施加到基底基板的前侧表面。 形成底部接触电源端子，并且将底部接触金属化层施加到底部接触层的表面。 去除金属化层的一部分，并在底部接触金属化层的表面上形成绝缘层。 在绝缘层的表面形成接地金属化馈通和功率金属化馈通。 顶层接触层序列被施加到绝缘层的表面，形成前侧接地端子和前端电源端子。 背面接地端子和背面电源端子形成在基底基板的背面。
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公开(公告)号：USD300359S
公开(公告)日：1989-03-21
申请号：US932541
申请日：1986-11-19
申请人： Michael G. Lee , James Hunsdale
设计人： Michael G. Lee , James Hunsdale
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公开(公告)号：US4677431A
公开(公告)日：1987-06-30
申请号：US768972
申请日：1985-08-23
申请人： Michael G. Lee
发明人： Michael G. Lee
摘要： An apparatus and method for smoothing the reproduction of digitized waveforms on a raster scan line display by providing control signals which increase and decrease the electron beam pattern along the scan line in a trapezoidal pattern which is representative of the amplitude of the sampled waveform along that scan line. A microprocessor provides a plurality of digital signals which define the slopes of the increasing and decreasing ramps of the trapazoids and their starting points along the scan line. The digital signals for an entire frame of scan lines are stored during the frame blanking interval of the display and are accessed for each scan line during the scan line blanking interval. The digital signals are stored in a random access memory (RAM) at raster scan line addresses provided by the processor through a scroll counter and at digital signal addresses provided through a display controller. During scan line blanking intervals the scroll counter incrementally steps through raster scan line addresses starting with the last address provided by the processor during the storing of the data.
摘要翻译： 一种用于通过提供控制信号来平滑光栅扫描线显示器上的数字化波形的再现的装置和方法，所述控制信号以梯形图案沿着扫描线增加和减少电子束图案，该梯形图案表示沿该扫描的采样波形的幅度 线。 微处理器提供多个数字信号，其限定沿着扫描线的陷波脉冲及其起始点的增加和减少斜坡的斜率。 扫描行的整帧的数字信号在显示器的帧消隐间隔期间被存储，并且在扫描行消隐间隔期间针对每条扫描线被访问。 数字信号通过滚动计数器和通过显示控制器提供的数字信号地址存储在由处理器提供的光栅扫描线地址处的随机存取存储器（RAM）中。 在扫描行消隐间隔期间，滚动计数器以数据存储的方式从处理器提供的最后一个地址开始逐步地逐步扫描光栅扫描行地址。
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公开(公告)号：US08633592B2
公开(公告)日：2014-01-21
申请号：US13190761
申请日：2011-07-26
申请人： Michael G. Lee , Chihiro Uchibori
发明人： Michael G. Lee , Chihiro Uchibori
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/11462 , H01L2224/1308 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2924/01029 , H01L2924/3511 , H01L2924/01047 , H01L2924/00014
摘要： In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.
摘要翻译： 在一个实施例中，集成电路（IC）芯片和衬底之间的互连结构包括多种材料。
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公开(公告)号：US07781867B2
公开(公告)日：2010-08-24
申请号：US11966254
申请日：2007-12-28
申请人： Michael G. Lee
发明人： Michael G. Lee
IPC分类号： H01L29/06
CPC分类号： H01L25/0657 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/05147 , H01L2224/05572 , H01L2224/056 , H01L2224/10135 , H01L2224/10165 , H01L2224/16 , H01L2224/81136 , H01L2224/81141 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06593 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/10157 , H01L2924/10253 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate.
摘要翻译： 提供一种半导体组件，其包括具有第一表面的第一基板。 第二衬底耦合到第一衬底并与第一衬底间隔开。 第二基板具有面向第一基板的第一表面的第二表面。 第二基板包括一组空腔。 一组非导电柱设置在第一基板的第一表面上并从第一基板的第一表面突出。 该非导电柱组被配置和定位成接合第二衬底的一组空腔以使第二衬底与第一衬底对准。
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50.发明授权Optical bumps for low-loss interconnection between a device and its supported substrate and related methods 失效用于器件与其支撑衬底之间低损耗互连的光学凸块及相关方法公开(公告)号：US07453058B2
公开(公告)日：2008-11-18
申请号：US11080200
申请日：2005-03-15
申请人： Michael G. Lee , Kishio Yokouchi
发明人： Michael G. Lee , Kishio Yokouchi
IPC分类号： H01J5/02
CPC分类号： H01L31/12
摘要： The present invention is directed to an apparatus and related methods related to an optical bump for optically coupling devices. An exemplary apparatus includes a first device, a second device, and at least one optical bump. The first device has a first surface including at least one first optically active area. The second device has a second surface including at least one second optically active area positioned in an opposed and spaced-apart relationship with respect to the at least one first optically active area. The first surface is separated from the second surface by a distance. The at least one optical bump is coupled to the first surface between the at least one first optically active area and the at least one second optically active area. The at least one optical bump has a height that is less than the distance between the first surface and the second surface. The at least one optical bump is configured to couple light between the at least one second optically active area and the at least one first optically active area.
摘要翻译： 本发明涉及一种与用于光耦合器件的光学凸块相关的装置和相关方法。 示例性装置包括第一装置，第二装置和至少一个光学凸块。 第一装置具有包括至少一个第一光学活性区域的第一表面。 第二装置具有第二表面，该第二表面包括相对于至少一个第一光学活性区域以相对且间隔开的关系定位的至少一个第二光学有源区域。 第一表面与第二表面分开一段距离。 所述至少一个光学凸块耦合到所述至少一个第一光学活性区域和所述至少一个第二光学有源区域之间的所述第一表面。 所述至少一个光学凸块的高度小于第一表面和第二表面之间的距离。 所述至少一个光学凸块配置成在所述至少一个第二光学有效区域和所述至少一个第一光学有源区域之间耦合光。
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