公开(公告)号：US10923494B2

公开(公告)日：2021-02-16

申请号：US16194946

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  David H. Wells ,  John D. Hopkins ,  Kevin Y. Titus

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L29/08 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11556 ,  H01L21/02 ,  H01L29/10 ,  H01L29/66 ,  H01L21/28 ,  H01L29/45 ,  H01L21/321

Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.

公开(公告)号：US20250062230A1

公开(公告)日：2025-02-20

申请号：US18766403

申请日：2024-07-08

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt

IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20

Abstract: A microelectronic device includes a first deck, a second deck, and a first conductive structure. The first deck has one or more memory cell strings and a stack of data lines operably connected to the one or more memory cell strings. Each of the one or more memory cell strings includes a first conductive contact. The second deck is vertically adjacent to the first deck and includes stacked tiers of conductive material defining a first interconnect structure. The first interconnect structure is operably connected to a data line of the stack of data lines. The first conductive structure is electrically coupled to the first conductive contact of the first deck and to the first interconnect structure of the second deck. Methods of forming the microelectronic device are also disclosed, as are memory devices, electronic signal processor devices, and electronic systems comprising such microelectronic devices.

公开(公告)号：US20250029924A1

公开(公告)日：2025-01-23

申请号：US18772808

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device, such as comprising NAND memory structures, can include a substrate with an arrangement of conductive interconnects. A corrugated support can be provided on the substrate, wherein the support comprises a planar first major surface and an opposed second major surface proximal to the substrate, the first major surface including a plurality of vias extending along a first direction, wherein the vias have an inlet at a first major surface of the support and an outlet at the second major surface of the support. An arrangement of flutes can be provided on the second major surface of the support. The flutes can extend along a second direction normal to the first direction. The flutes are separated by voids, and the vias terminate in the voids.

公开(公告)号：US12041775B2

公开(公告)日：2024-07-16

申请号：US17933227

申请日：2022-09-19

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H10B43/27 ,  H01L21/768

CPC classification number: H10B43/27 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US12040223B2

公开(公告)日：2024-07-16

申请号：US17141722

申请日：2021-01-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  John D. Hopkins ,  Madison D. Drake

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/7682 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/53257 ,  H01L23/5329 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US12010847B2

公开(公告)日：2024-06-11

申请号：US17691993

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H10B43/27 ,  H01L23/48 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US20240112734A1

公开(公告)日：2024-04-04

申请号：US18529731

申请日：2023-12-05

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D. Drake

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US11887667B2

公开(公告)日：2024-01-30

申请号：US17397603

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Albert Fayrushin ,  Matthew J. King ,  Madison D Drake

IPC: G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/66795 ,  H01L29/7851 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A variety of applications can include memory devices designed to provide enhanced gate-induced-drain-leakage (GIDL) current during memory erase operations. The enhanced operation can be provided by enhancing the electric field in the channel structures of select gate transistors to strings of memory cells. The channel structures can be implemented as a segmented portion for drains and a portion opposite a gate. The segmented portion includes one or more fins and one or more non-conductive regions with both fins and non-conductive regions extending vertically from the portion opposite the gate. Variations of a border region for the portion opposite the gate with the segmented portion can include fanged regions extending from the fins into the portion opposite the gate or rounded border regions below the non-conductive regions. Such select gate transistors can be formed using a single photo mask process. Additional devices, systems, and methods are discussed.

公开(公告)号：US20230197608A1

公开(公告)日：2023-06-22

申请号：US17644937

申请日：2021-12-17

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Amber Thompson ,  Shruthi Kumara Vadivel

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A microelectronic device includes a stack structure having a vertically alternating sequence of conductive structures and insulating structures arranged in tiers. The stack structure further includes a first block having first stadium structures having steps having horizontal ends of the tiers, an arrangement of the first stadium structures ascending from a lowermost first stadium structure to an uppermost first stadium structure in a first horizontal direction and a second block neighboring the first block in a second horizontal direction orthogonal to the first horizontal direction and having second stadium structures having additional steps having additional horizontal ends of the tiers, an arrangement of second stadium structures descending from an uppermost second stadium structure to a lowermost second stadium structure in the first horizontal direction. Related methods and electronic systems are also disclosed.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.