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    MEMORY DEVICE INCLUDING SELF-ALIGNED CONDUCTIVE CONTACTS
    41.
    发明申请
    MEMORY DEVICE INCLUDING SELF-ALIGNED CONDUCTIVE CONTACTS 有权

    公开(公告)号：US20220199467A1

    公开(公告)日：2022-06-23

    申请号：US17127823

    申请日：2020-12-18

    Applicant: Micron Technology, Inc.

    Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

    Devices and methods including an etch stop protection material
    43.
    发明授权
    Devices and methods including an etch stop protection material 有权

    公开(公告)号：US10573721B2

    公开(公告)日：2020-02-25

    申请号：US15470617

    申请日：2017-03-27

    Applicant: Micron Technology, Inc.

    Inventor： John Hopkins ,  Darwin Franseda Fan

    IPC: H01L29/49 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

    Memory including blocking dielectric in etch stop tier
    49.
    发明授权
    Memory including blocking dielectric in etch stop tier 有权
    存储器包括蚀刻停止层中的阻挡电介质

    公开(公告)号：US09559109B2

    公开(公告)日：2017-01-31

    申请号：US14746515

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  John Hopkins ,  Srikant Jayanti

    IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788

    CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

    Abstract translation: 垂直记忆及其制备方法一般在此讨论。 在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。 蚀刻停止层可以包括邻近柱的阻挡电介质。 在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

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