公开(公告)号：US20240338138A1

公开(公告)日：2024-10-10

申请号：US18746987

申请日：2024-06-18

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US12026385B2

公开(公告)日：2024-07-02

申请号：US17952927

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

公开(公告)号：US11868639B2

公开(公告)日：2024-01-09

申请号：US17350866

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10 ,  G06F11/14

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1068 ,  G06F11/1402 ,  G11C29/52

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

公开(公告)号：US11847065B2

公开(公告)日：2023-12-19

申请号：US17410842

申请日：2021-08-24

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Mark Ish ,  Peng Xu

IPC: G06F12/12 ,  G06F3/06

CPC classification number: G06F12/12 ,  G06F3/0608 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0673

Abstract: A request to perform a program operation at a memory device is received. Whether a firmware block record is to be modified to correspond with a device block record is determined based on parameters associated with the program operation. The firmware block record tracks entries of the device block record. Responsive to determining that the firmware block record is to be modified, the firmware block record is modified to correspond with the device block record.

公开(公告)号：US11763895B2

公开(公告)日：2023-09-19

申请号：US17873850

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Michele Piccardi ,  Qing Liang

IPC: G11C16/04 ,  G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

CPC classification number: G11C16/30 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F12/0875 ,  G11C16/10 ,  G06F2212/603 ,  G11C16/0483

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

公开(公告)号：US11720286B2

公开(公告)日：2023-08-08

申请号：US17516009

申请日：2021-11-01

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.

公开(公告)号：US20230230624A1

公开(公告)日：2023-07-20

申请号：US17415657

申请日：2021-01-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jiangang Wu ,  Lei Zhou ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Qisong Lin

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C7/1096 ,  G11C8/08 ,  G11C8/14

Abstract: A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.

公开(公告)号：US11461158B2

公开(公告)日：2022-10-04

申请号：US15733561

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Shao Chun Shi

IPC: G06F11/00 ,  G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.

公开(公告)号：US20220246222A1

公开(公告)日：2022-08-04

申请号：US17726112

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Scott Anthony Stoller ,  Kevin R. Brandt ,  Qisong Lin

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/16

Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

公开(公告)号：US20220236871A1

公开(公告)日：2022-07-28

申请号：US17160144

申请日：2021-01-27

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.