公开(公告)号：US11665893B2

公开(公告)日：2023-05-30

申请号：US15255967

申请日：2016-09-02

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun Jeff Hu ,  Haitao Liu

IPC: H01L27/11556 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11524 ,  H01L23/528 ,  H01L29/45

CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

公开(公告)号：US20220302015A1

公开(公告)日：2022-09-22

申请号：US17837923

申请日：2022-06-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10 ,  G11C13/00 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/24 ,  H01L45/00 ,  H01L27/1157

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US10651315B2

公开(公告)日：2020-05-12

申请号：US13716287

申请日：2012-12-17

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Hongbin Zhu ,  Gordon A Haller ,  Roger W. Lindsay ,  Andrew Bicksler ,  Brian J. Cleereman ,  Minsoo Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/225 ,  H01L27/11556 ,  H01L29/788 ,  H01L27/11568 ,  H01L27/11565 ,  H01L27/11519 ,  H01L23/528 ,  H01L23/532 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/535 ,  H01L29/66 ,  H01L29/792

Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.

公开(公告)号：US20160284728A1

公开(公告)日：2016-09-29

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。

公开(公告)号：US20150129935A1

公开(公告)日：2015-05-14

申请号：US14602559

申请日：2015-01-22

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  H01L27/10

CPC classification number: H01L27/11582 ,  G11C13/0007 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L23/52 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/249 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成，并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部，并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地，在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

公开(公告)号：US20130154104A1

公开(公告)日：2013-06-20

申请号：US13771117

申请日：2013-02-20

Applicant: Micron Technology, Inc.

Inventor： Roger W. Lindsay

IPC: H01L23/498

CPC classification number: H01L23/498 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/4824 ,  H01L23/528 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.

Abstract translation: 集成电路包括电路，耦合到电路的第一导体，耦合到第一导体的导电焊盘以及耦合到导电焊盘的第二导体。 第二导体将是浮动的，但是其耦合到导电焊盘。 第二导体可以与第一导体隔开一段距离，该距离基本上等于由形成第一和第二导体的导电材料上的单个侧壁间隔物合并形成的合并间隔物的宽度。

公开(公告)号：US20250118653A1

公开(公告)日：2025-04-10

申请号：US18981288

申请日：2024-12-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending extend farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US20250029924A1

公开(公告)日：2025-01-23

申请号：US18772808

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Roger W. Lindsay

IPC: H01L23/528 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device, such as comprising NAND memory structures, can include a substrate with an arrangement of conductive interconnects. A corrugated support can be provided on the substrate, wherein the support comprises a planar first major surface and an opposed second major surface proximal to the substrate, the first major surface including a plurality of vias extending along a first direction, wherein the vias have an inlet at a first major surface of the support and an outlet at the second major surface of the support. An arrangement of flutes can be provided on the second major surface of the support. The flutes can extend along a second direction normal to the first direction. The flutes are separated by voids, and the vias terminate in the voids.

公开(公告)号：US11903211B2

公开(公告)日：2024-02-13

申请号：US17647238

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H10B41/41

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20230117100A1

公开(公告)日：2023-04-20

申请号：US18083991

申请日：2022-12-19

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lise M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H10B43/27 ,  H01L23/528 ,  H10B43/10 ,  H01L23/522 ,  H01L21/02 ,  H10B51/20 ,  H01L21/67

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.