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    DETECTION CIRCUITRY TO DETECT A DECK OF A MEMORY ARRAY
    41.
    发明申请
    DETECTION CIRCUITRY TO DETECT A DECK OF A MEMORY ARRAY 有权

    公开(公告)号：US20210319846A1

    公开(公告)日：2021-10-14

    申请号：US16847181

    申请日：2020-04-13

    Applicant: Micron Technology, Inc.

    Inventor： Bret Addison Johnson ,  Vijayakrishna J. Vankayala

    IPC: G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/36

    Abstract: As described, a device may include detection circuitry to detect a deck of a memory array. The deck may include a conductive identifier coupled between a logic high voltage node and the detection circuitry a control circuit coupled to the detection circuit. The control circuit may perform operations including transmitting a test enable signal to the detection circuitry. The detection circuitry may generate a valid signal indicative of an existence of the conductive identifier of the deck in response to the test enable signal. The operations may also include the control circuit receiving the valid signal from the detection circuitry and adjusting a memory operation associated with the memory array based at least in part on the valid signal.

    SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND RELATED SYSTEMS, METHODS, AND APPARATUSES
    42.
    发明申请
    SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND RELATED SYSTEMS, METHODS, AND APPARATUSES 有权

    公开(公告)号：US20210286739A1

    公开(公告)日：2021-09-16

    申请号：US16819914

    申请日：2020-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Vijayakrishna J. Vankayala

    IPC: G06F13/16 ,  G06F11/10 ,  H01L25/065

    Abstract: Separate inter-die connectors for data and error correction information and related systems, methods, and devices are disclosed. An apparatus includes a master die, a target die including data storage elements, inter-die data connectors, and inter-die error correction connectors. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct data between the master die and the target die. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are separate from the inter-die data connectors. The inter-die error correction connectors are configured to conduct error correction information corresponding to the data between the master die and the target die.

    Apparatuses and methods for command signal delay
    44.
    发明授权
    Apparatuses and methods for command signal delay 有权

    公开(公告)号：US10699768B2

    公开(公告)日：2020-06-30

    申请号：US16104124

    申请日：2018-08-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vijayakrishna J. Vankayala ,  Jason M. Brown

    IPC: G11C11/4076 ,  G11C11/408

    Abstract: Apparatuses and methods for a command decoder delay are disclosed. An example apparatus includes a command decoder which may receive memory access command. The command decoder may provide an output command based on the memory access command to a command path at a first time. The command decoder may also provide the output command to a data path at a second time, wherein the second time is delayed relative to the first time.

    Command-in-pipeline counter for a memory device
    45.
    发明授权
    Command-in-pipeline counter for a memory device 有权

    公开(公告)号：US10684797B2

    公开(公告)日：2020-06-16

    申请号：US16119766

    申请日：2018-08-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Vijayakrishna J. Vankayala

    IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  H03K23/40 ,  H03K19/20

    Abstract: Memory devices and methods utilize pipelines to process or control timing of commands received by the memory device. They may also use tracking circuitry configured to determine whether one or more of the commands are in the pipeline. The tracking circuitry includes an input counter configured to count commands entering into the pipeline and an output counter configured to count commands exiting the pipeline. Furthermore, the tracking circuitry includes comparison circuitry configured to compare values in the input counter and the output counter and to output a command-in-pipeline signal indicative of the one or more commands being in the pipeline when the values in the input counter and the output counter differ.

    DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE
    47.
    发明公开
    DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE 审中-公开

    公开(公告)号：US20240223196A1

    公开(公告)日：2024-07-04

    申请号：US18607999

    申请日：2024-03-18

    Applicant: Micron Technology, Inc.

    Inventor： Vijayakrishna J. Vankayala

    IPC: H03L7/191 ,  G11C7/10 ,  H03K19/20 ,  H03L7/197

    CPC classification number: H03L7/191 ,  G11C7/1039 ,  H03K19/20 ,  H03L7/1976

    Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.

    Apparatuses and method for trimming input buffers based on identified mismatches
    49.
    发明授权
    Apparatuses and method for trimming input buffers based on identified mismatches 有权

    公开(公告)号：US11810641B2

    公开(公告)日：2023-11-07

    申请号：US16926505

    申请日：2020-07-10

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Christian N. Mohr ,  Jennifer E. Taylor ,  Vijayakrishna J. Vankayala

    IPC: G11C7/10 ,  G11C11/4093 ,  H03F3/45

    CPC classification number: G11C7/1084 ,  G11C7/1096 ,  G11C11/4093 ,  H03F3/45475

    Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

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