中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

221 records (took 0.043 seconds)

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    44.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20250037768A1

    公开(公告)日：2025-01-30

    申请号：US18919650

    申请日：2024-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

    IPC: G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
    45.
    发明申请
    Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20240381638A1

    公开(公告)日：2024-11-14

    申请号：US18784152

    申请日：2024-07-25

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee

    IPC: H10B43/10 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings. A conductive material is formed in the void space directly above and directly electrically coupled to the lower portion of the individual digitlines to form an upper portion thereof. Other embodiments, including structure independent of method, are disclosed.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    46.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12082409B2

    公开(公告)日：2024-09-03

    申请号：US17674289

    申请日：2022-02-17

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee

    IPC: G11C11/34 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  G11C16/04 ,  H10B41/35 ,  H10B43/35

    CPC classification number: H10B43/10 ,  H10B41/10 ,  H10B41/27 ,  H10B43/27 ,  G11C16/0483 ,  H10B41/35 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers having channel-material strings therein. Walls are formed above insulating material that is directly above the channel-material strings. Void space is laterally-between immediately-adjacent of the walls and that comprises a longitudinal outline of individual digitlines to be formed. Spaced openings are in the insulating material directly below the void space. Relative to the walls, a conductive metal nitride is selectively deposited in the void space, in the spaced openings, and atop the insulating material laterally-between the walls and the spaced openings to form a lower portion of the individual digitlines laterally-between the immediately-adjacent walls. The conductive metal nitride that is in individual of the spaced openings is directly electrically coupled to individual of the channel-material strings. A conductive material is formed in the void space directly above and directly electrically coupled to the lower portion of the individual digitlines to form an upper portion thereof. Other embodiments, including structure independent of method, are disclosed.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    47.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12058861B2

    公开(公告)日：2024-08-06

    申请号：US17409434

    申请日：2021-08-23

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Jordan D. Greenlee

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Strings of memory cells comprise channel-material-string constructions that extend through the insulative tiers and the conductive tiers into the conductor tier. The channel material of the channel-material-string constructions directly electrically couples to conductor material of the conductor tier. The conductor tier comprises islands comprising material of different composition from that of the conductor material of the conductor tier that surrounds individual of the islands. The islands are directly against bottoms of the channel-material-string constructions. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. Other aspects, including method, are disclosed.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    50.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240224505A1

    公开(公告)日：2024-07-04

    申请号：US18527091

    申请日：2023-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

    IPC: H10B12/00

    CPC classification number: H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

Patent Agency Ranking