公开(公告)号：US08455270B2

公开(公告)日：2013-06-04

申请号：US12561618

申请日：2009-09-17

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L24/94 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14

摘要： A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.

摘要翻译： 形成三维（3D）模具的过程。 针对通过（良好的模具）或失败（坏模具）预定测试标准的模具测试多个晶片。 两个测试的晶片彼此靠近放置。 以这样的方式对晶片进行对准，以便使两个晶片之间对准的良好裸片的数量最大化。 然后将两个晶片结合在一起并切成多个粘结好的模具的各个叠层。

公开(公告)号：US08415238B2

公开(公告)日：2013-04-09

申请号：US12687282

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： H01L21/425 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.

摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露衬底层上的第一平面区域，蚀刻暴露的平面区域以形成在结构中具有第一深度的空腔，将光致抗蚀剂的第二部分去除 在衬底层上露出第二平面区域，在第二平面区域中形成掺杂部分，并且蚀刻腔体以暴露结构中的第一导体和掺杂部分以暴露结构中的第二导体。

公开(公告)号：US08399180B2

公开(公告)日：2013-03-19

申请号：US12687289

申请日：2010-01-14

申请人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

发明人： Mukta G. Farooq ,  Ramona Kei ,  Emily R. Kinser ,  Anthony D. Lisi ,  Richard Wise ,  Hakeem Yusuff

IPC分类号： G03F7/26

CPC分类号： H01L21/76898 ,  H01L21/3085 ,  H01L25/0657 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.

摘要翻译： 公开了一种方法，其包括在结构的衬底上图案化光致抗蚀剂层，去除光致抗蚀剂层的第一部分以暴露衬底的第一区域，蚀刻第一区域以形成具有第一深度的空腔， 光致抗蚀剂的一部分以暴露衬底的附加区域，并且蚀刻该腔以暴露结构中的第一导体和附加区域以暴露该结构中的第二导体。

公开(公告)号：US20120292786A1

公开(公告)日：2012-11-22

申请号：US13569231

申请日：2012-08-08

申请人： Richard P. Volant ,  Mukta G. Farooq ,  Kevin S. Petrarca

发明人： Richard P. Volant ,  Mukta G. Farooq ,  Kevin S. Petrarca

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/16 ,  H01L24/29 ,  H01L24/82 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/29 ,  H01L2224/29298 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/05552 ,  H01L2924/00

摘要： A microelectronic assembly having a through hole extending through a first wafer (or chip) and a second wafer (or chip) are provided. The first and second wafers (or chips) have confronting faces and metallic features at the faces which are joined together to assemble the first and second wafers (or chips) leaving a gap between the confronting faces. A hole is etched in the first wafer (or chip), then material is sputtered to form a wall of material in the gap between wafers (or chips). Etching continues to extend the hole into or through the second wafer (or chip). The hole is filled to form a substantially vertical through silicon conductive via.

摘要翻译： 提供具有延伸穿过第一晶片（或芯片）和第二晶片（或芯片）的通孔的微电子组件。 第一和第二晶片（或芯片）在面处具有面对面和金属特征，所述表面和金属特征被连接在一起以组装在相对面之间留下间隙的第一和第二晶片（或芯片）。 在第一晶片（或芯片）中蚀刻孔，然后溅射材料以在晶片（或芯片）之间的间隙中形成材料壁。 蚀刻继续将孔扩展到第二晶片（或芯片）中或通过第二晶片（或芯片）。 该孔被填充以形成基本垂直的通过硅的导电通孔。

公开(公告)号：US20120258589A1

公开(公告)日：2012-10-11

申请号：US13495092

申请日：2012-06-13

申请人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

发明人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage.

摘要翻译： 一种制造在硅衬底内形成独特的同轴或三轴互连的穿硅通孔（TSV）结构的方法。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。

公开(公告)号：US08236610B2

公开(公告)日：2012-08-07

申请号：US12471656

申请日：2009-05-26

申请人： Louis Lu-Chen Hsu ,  Kangguo Cheng ,  Timothy J. Dalton ,  Mukta G. Farooq ,  John A. Fitzsimmons

发明人： Louis Lu-Chen Hsu ,  Kangguo Cheng ,  Timothy J. Dalton ,  Mukta G. Farooq ,  John A. Fitzsimmons

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/14 ,  H01L21/6836 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/06183 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14183 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16137 ,  H01L2224/16147 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

摘要翻译： 公开了能够形成半导体芯片连接的系统和方法。 在一个实施例中，半导体芯片包括具有一对相对侧面的多面体形状的主体; 以及沿着在多面体形状的一对相对侧之间延伸的一侧延伸的焊料构件。

公开(公告)号：US20120175789A1

公开(公告)日：2012-07-12

申请号：US12987202

申请日：2011-01-10

申请人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

发明人： Mukta G. Farooq ,  Troy L. Graves-Abe ,  Robert Hannon ,  Emily R. Kinser ,  William F. Landers ,  Kevin S. Patrarca ,  Richard P. Volant ,  Kevin R. Winstel

IPC分类号： H01L23/544 ,  H01L21/02

CPC分类号： H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/8385 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2224/83

摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

公开(公告)号：US20120119363A1

公开(公告)日：2012-05-17

申请号：US13357146

申请日：2012-01-24

申请人： Mukta G. Farooq

发明人： Mukta G. Farooq

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/013

摘要： Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.

摘要翻译： 使用金属添加到Sn基无铅C4球以提高可靠性。 具体地说，在Sn中溶解度低的金属以相当于原子浓度小于1％的少量加入。 由于添加的金属的溶解度低，在C4球的固化期间形成微细的析出物，其作为在固化的C4球中形成多个晶粒的成核位置。 微细的沉淀物也通过堵塞晶界抑制快速的晶粒生长，并且作为在C4球中钉扎位错的试剂。 晶粒边界使得能够在半导体芯片和C4球的封装的热循环期间减轻应力的晶界滑动。 此外，微细沉淀物由于其固着性而防止沿着晶界的电迁移。

公开(公告)号：US08128868B2

公开(公告)日：2012-03-06

申请号：US12605393

申请日：2009-10-26

申请人： Mukta G. Farooq

发明人： Mukta G. Farooq

IPC分类号： C22C13/00

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/013

摘要： Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature.

摘要翻译： 使用金属添加到Sn基无铅C4球以提高可靠性。 具体地说，在Sn中溶解度低的金属以相当于原子浓度小于1％的少量加入。 由于添加的金属的溶解度低，在C4球的固化期间形成微细的析出物，其作为在固化的C4球中形成多个晶粒的成核位置。 微细的沉淀物也通过堵塞晶界抑制快速的晶粒生长，并且作为在C4球中钉扎位错的试剂。 晶粒边界使得能够在半导体芯片和C4球的封装的热循环期间减轻应力的晶界滑动。 此外，微细沉淀物由于其固着性而防止沿着晶界的电迁移。

公开(公告)号：US20110140245A1

公开(公告)日：2011-06-16

申请号：US13031195

申请日：2011-02-19

申请人： MICHAEL W. LANE ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D.W. Melville

发明人： MICHAEL W. LANE ,  Xiao Hu Liu ,  Thomas M. Shaw ,  Mukta G. Farooq ,  Robert Hannon ,  Ian D.W. Melville

IPC分类号： H01L23/58

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L21/78 ,  H01L23/5329 ,  H01L23/562 ,  H01L23/585 ,  H01L24/90 ,  H01L2224/73203 ,  H01L2224/90 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/18301 ,  H01L2924/00

摘要： A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

摘要翻译： 半导体产品包括具有顶表面和包括半导体芯片的底表面的半导体衬底。 半导体衬底具有顶表面和周边。 在周边的芯片中形成屏障。 在深度隔离沟槽（UDIT）中切割在芯片的上表面，其在周边和屏障之间向下延伸。 在形成屏障和UDIT之前，在衬底上形成具有低k pSICOH电介质和硬掩模层的ILD结构。 除了UDIT之外，ILD结构互连结构可以向下凹入底层。