公开(公告)号：US5781062A

公开(公告)日：1998-07-14

申请号：US582416

申请日：1996-01-03

申请人： Koichiro Mashiko ,  Kimio Ueda ,  Hiroaki Suzuki ,  Hiroyuki Morinaka

发明人： Koichiro Mashiko ,  Kimio Ueda ,  Hiroaki Suzuki ,  Hiroyuki Morinaka

IPC分类号： G11C5/14 ,  G11C11/407 ,  H03K19/00 ,  H03K19/0948 ,  G05F1/10

CPC分类号： H03K19/0016 ,  G11C5/14 ,  G11C5/147 ,  H01L2924/0002

摘要： A logic circuit (L.sub.i) is connected between a virtual power supply line (VDDV) connected to an actual power supply (VDD) through a PMOS transistor (Q1) and a virtual grounding line (GNDV) connected to an actual ground (GND) through an NMOS transistor (Q2). During an active period, the transistors (Q1, Q2) are constantly conducting, and the virtual power supply line (VDDV) and virtual grounding line (GNDV) are at the power supply potential (VDD) and ground potential (GND), respectively. During a standby period, the transistors (Q1, Q2) periodically repeat conduction/non-conduction to charge and discharge the virtual power supply line (VDDV) and virtual grounding line (GNDV), suppressing power consumption while preventing loss of information held by the logic circuit (L.sub.i).

摘要翻译： 逻辑电路（Li）通过PMOS晶体管（Q1）连接到与实际电源（VDD）连接的虚拟电源线（VDDV）和连接到实际地线（GND）的虚拟接地线（GNDV）之间通过 一个NMOS晶体管（Q2）。 在激活期间，晶体管（Q1，Q2）恒定导通，虚拟电源线（VDDV）和虚拟接地线（GNDV）分别处于电源电位（VDD）和接地电位（GND）。 在待机期间，晶体管（Q1，Q2）周期性地重复导通/非导通，对虚拟电源线（VDDV）和虚拟接地线（GNDV）进行充电和放电，从而抑制功耗，同时防止由 逻辑电路（Li）。

公开(公告)号：US5394511A

公开(公告)日：1995-02-28

申请号：US131581

申请日：1993-10-05

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N99/00 ,  H01L27/10 ,  G06G7/12 ,  G06F7/00

CPC分类号： G06N3/063

摘要： A neural network device includes internal data input lines, internal data output lines, coupling elements provided at the connections of the internal data input lines and the internal data output lines. The coupling elements couple, with specific programmable coupling strengths, the associated internal data input lines to the associated internal data output lines. In a program mode, the internal data output lines serve as signal lines for transmitting the coupling strength information. Each of the coupling elements includes storage elements, circuitry for writing a signal potential on an associated internal data output line, and circuitry for supplying a stored signal for a storage element into an associated internal data output line.

摘要翻译： 神经网络设备包括内部数据输入线，内部数据输出线，在内部数据输入线和内部数据输出线的连接处提供的耦合元件。 耦合元件具有特定的可编程耦合强度，将相关联的内部数据输入线耦合到相关联的内部数据输出线。 在程序模式中，内部数据输出线用作发送耦合强度信息的信号线。 每个耦合元件包括存储元件，用于在相关联的内部数据输出线上写入信号电位的电路，以及用于将存储元件的存储信号提供到相关联的内部数据输出线中的电路。

公开(公告)号：US4988891A

公开(公告)日：1991-01-29

申请号：US406651

申请日：1989-09-13

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G06G7/60 ,  G06F15/18 ,  G06N3/04 ,  G06N3/067 ,  G06N99/00

CPC分类号： G06N3/0675

摘要： A semiconductor neural network constructed in accordance with models of vital nerve cells has photosensitive elements as coupling elements providing degrees of coupling between neurons which are modeled vital nerve cells. The conductance values of the photosensitive elements can be set by light. Due to such structure, not only the degrees of coupling of all the coupling elements can be simultaneously programmed but signal lines for programming the degrees of coupling can be eliminated in the network, whereby a semiconductor neural network having a high degree of integration can be implemented without additional complicating fabrication steps.

摘要翻译： 根据重要神经细胞模型构建的半导体神经网络具有作为耦合元件的光敏元件，其提供被建模的重要神经细胞的神经元之间的偶联程度。 感光元件的电导值可以通过光来设定。 由于这样的结构，不仅可以同时对所有耦合元件的耦合度进行编程，而且可以在网络中消除用于编程耦合度的信号线，由此可以实现具有高集成度的半导体神经网络 没有额外的复杂的制造步骤。

公开(公告)号：US4912678A

公开(公告)日：1990-03-27

申请号：US247286

申请日：1988-09-22

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： G11C11/401 ,  G11C11/406

CPC分类号： G11C11/406

摘要： A dynamic random access memory (DRAM) comprises a divided plurality of memory array blocks. Each memory array block comprises a memory array having memory cells and a sense amplifier. In refresh operation, activating signals for activating each of the sense amplifiers are outputted. The output timings of the activating signals are different from each other, so that each of the sense amplifiers are activated at different timings. Consequently, a peak value of the current consumed by the activation of the sense amplifiers can be reduced.

摘要翻译： 动态随机存取存储器（DRAM）包括划分的多个存储器阵列块。 每个存储器阵列块包括具有存储器单元和读出放大器的存储器阵列。 在刷新操作中，输出激活每个读出放大器的激活信号。 激活信号的输出定时彼此不同，使得每个读出放大器在不同的定时被激活。 因此，可以减少由感测放大器的激活消耗的电流的峰值。

公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

申请人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12 ,  H03F3/45

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。

公开(公告)号：US20070018867A1

公开(公告)日：2007-01-25

申请号：US11408951

申请日：2006-04-24

申请人： Masafumi Uemori ,  Haruo Kobayashi ,  Tomonari Ichikawa ,  Koichiro Mashiko

发明人： Masafumi Uemori ,  Haruo Kobayashi ,  Tomonari Ichikawa ,  Koichiro Mashiko

IPC分类号： H03M3/00

CPC分类号： H03M3/372 ,  H03M3/402 ,  H03M3/422 ,  H03M3/454 ,  H03M3/496

摘要： A continuous-time band-pass ΔΣ AD modulator subtracts an analog signal from a DA converter from an inputted analog signal, outputs an analog signal having a subtraction result to an AD converter via a continuous-time analog band-pass filter, outputs a digital signal from the AD converter to the DA converter, and outputs the same digital signal as a digital signal subjected to a band-pass ΔΣ AD modulation processing. The highest input frequency “fin” of the inputted analog signal is substantially set to three-fourths of a sampling frequency “fs”. The DA converter is configured to convert the inputted digital signal into the analog signal, and outputs the analog signal, which is inverted or not in response to a value of the inputted digital signal and has an amplitude of substantially zero and a gradient of substantially zero at a timing k/(2fs).

摘要翻译： 连续时间带通DeltaSigma AD调制器从输入的模拟信号中减去来自DA转换器的模拟信号，经由连续时间模拟带通滤波器将具有减法结果的模拟信号输出到AD转换器，输出数字 信号从AD转换器传送到DA转换器，并输出与进行带通DeltaSigma AD调制处理的数字信号相同的数字信号。 输入的模拟信号的最高输入频率“fin”基本上被设置为采样频率“fs”的四分之三。 DA转换器被配置为将输入的数字信号转换为模拟信号，并且输出模拟信号，该模拟信号被反相或不响应于输入的数字信号的值，并且具有基本为零的幅度和基本为零的梯度 在k /（2fs）的时刻。

公开(公告)号：US06249690B1

公开(公告)日：2001-06-19

申请号：US09198527

申请日：1998-11-24

申请人： Koichiro Mashiko

发明人： Koichiro Mashiko

IPC分类号： H04B138

CPC分类号： H02J7/0027 ,  H02J7/00 ,  H02J2007/0096 ,  H04B1/3883 ,  H04M1/7253 ,  H04M1/727

摘要： A portable information system having an information registration function achieves reduction in manufacturing cost and power consumption. By connecting portable information equipment (1) and a battery charger (10) to be chargeable, signal transmission becomes possible between a micro controller (2) in the portable information equipment (1) and a micro controller (11) in the battery charger (10). Under the control of the micro controllers (2, 11), information management operation is automatically performed during charging. The operation includes backup processing in which personal information stored in a storage portion (3) in the portable information equipment (1) is transferred to a storage portion (12) in the battery charger (10) as backup information, and restore processing in which the backup information stored in the storage portion (12) is transferred to the storage portion (3) as the personal information.

公开(公告)号：US6005422A

公开(公告)日：1999-12-21

申请号：US773313

申请日：1996-12-24

申请人： Hiroyuki Morinaka ,  Hiroshi Makino ,  Kimio Ueda ,  Koichiro Mashiko

发明人： Hiroyuki Morinaka ,  Hiroshi Makino ,  Kimio Ueda ,  Koichiro Mashiko

IPC分类号： G06F13/38 ,  G06F1/32 ,  G06F5/00 ,  H03K19/00 ,  H04L25/02 ,  H03K1/04 ,  G06F1/08

CPC分类号： G06F7/523 ,  G06F1/32 ,  G06F5/00 ,  H03K19/0008

摘要： A semiconductor integrated circuit and a method for reducing the consumed power are provided. A comparator outputs bits having the same level, which correspond to each other, of a last input stored in a register and a current input that acts as an input signal. A zero counter counts the number of the bits having the same level output from the comparator. If the number of the bits having the same level is smaller than a predetermined number, the current input is not similar to the last input. Consequently, an instruction is given to a flip-flop to invert the current input. The inverted current input becomes similar to the last input. Thus, the consumed power of a logic can be reduced.

摘要翻译： 提供半导体集成电路和降低功耗的方法。 比较器输出存储在寄存器中的最后一个输入和作为输入信号的当前输入的具有相同电平的位。 零计数器对比较器具有相同电平输出的位数进行计数。 如果具有相同电平的位的数量小于预定数量，则当前输入与最后一个输入不相似。 因此，给触发器指示反转当前输入。 反相电流输入变得与最后一个输入相似。 因此，可以减少逻辑的消耗功率。

公开(公告)号：US5859800A

公开(公告)日：1999-01-12

申请号：US949821

申请日：1997-10-14

申请人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

发明人： Kimio Ueda ,  Hiroyuki Morinaka ,  Koichiro Mashiko

IPC分类号： H03K3/356 ,  G11C7/10 ,  H03K3/037 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1093 ,  H03K3/356121 ,  H03K3/356173

摘要： A highly reliable data holding circuit with a reduced circuit area and reduced power consumption is disclosed. Output terminals (DO, DOB) are connected to input terminals (DI, DIB) receiving signals at H and L levels (potentials VDD and GND) in mutually exclusive relation through transistors (MN2, MN1) and inverters (INV1, INV2). Input terminals of the inverters (INV1, INV2) are connected to power supplies (VDD) through transistors (MP2, MP1) having gate electrodes connected to output terminals of the inverters (INV2, INV1), respectively. The transistors (MN2, MN1) cause a voltage drop of the signals to be applied to the inverters (INV1, INV2) by the amount of a threshold voltage (Vthn). One of the transistors (MP1, MP2) which receives a signal at L level at its control terminal provides a potential (VDD) to the input terminal of one of the inverters (INV1, INV2) which is to output a signal at L level, compensating for the voltage drop by the amount of the threshold voltage (Vthn).

摘要翻译： 公开了一种具有降低的电路面积和降低的功耗的高度可靠的数据保持电路。 输出端子（DO，DOB）通过晶体管（MN2，MN1）和反相器（INV1，INV2）以H和L电平（电位VDD和GND）的互斥关系连接到输入端子（DI，DIB）。 反相器（INV1，INV2）的输入端分别通过连接到反相器（INV2，INV1）的输出端的栅电极的晶体管（MP2，MP1）连接到电源（VDD）。 晶体管（MN2，MN1）使信号的电压降到施加到反相器（INV1，INV2）的量的阈值电压（Vthn）。 在其控制端子处接收到L电平的信号的晶体管（MP1，MP2）中的一个为向L电平输出信号的反相器（INV1，INV2）中的一个的输入端提供电位（VDD） 通过阈值电压（Vthn）的量来补偿电压降。