公开(公告)号：US20050127502A1

公开(公告)日：2005-06-16

申请号：US10737496

申请日：2003-12-16

申请人： Daniel Lee ,  Chender Huang ,  C. H. Lee

发明人： Daniel Lee ,  Chender Huang ,  C. H. Lee

IPC分类号： H01L23/34 ,  H01L23/36 ,  H01L23/373

CPC分类号： H01L23/36 ,  H01L23/3735 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/16195

摘要： A microelectronic package comprising a device substrate having first and second opposing surfaces and comprising a plurality of microelectronic devices. The microelectronic package also includes a plurality of electrically conductive members coupled to corresponding ones of the plurality of microelectronics device and extending away from the first surface. A thermally conductive layer is located on the second surface of the device substrate, and a package substrate is coupled to the device substrate, the package substrate having a plurality of electrically conductive traces coupled to corresponding ones of the plurality of electrically conductive members.

摘要翻译： 一种微电子封装，其包括具有第一和第二相对表面并且包括多个微电子器件的器件衬底。 微电子封装还包括耦合到多个微电子器件中的相应微电子器件并且远离第一表面延伸的多个导电构件。 导热层位于器件衬底的第二表面上，并且封装衬底耦合到器件衬底，封装衬底具有耦合到多个导电构件中的相应导电构件的多个导电迹线。

公开(公告)号：US6091251A

公开(公告)日：2000-07-18

申请号：US888448

申请日：1997-07-07

申请人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

发明人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC分类号： G01R31/2893 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H05K3/4007 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15787 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

摘要： A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

摘要翻译： 用于离散TAB模具的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分包含插入模具的腔体。 当组装两个半部时，夹具与模具建立电接触，并与老化烘箱连接。 在老化和电气测试完成之前，测试夹具不需要打开。 夹具允许在组装之前对模具进行表征。

公开(公告)号：US06998860B1

公开(公告)日：2006-02-14

申请号：US09612696

申请日：2000-07-10

申请人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

发明人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

IPC分类号： G01R31/02 ,  G01R31/28

CPC分类号： G01R31/2875

摘要： A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

摘要翻译： 用于离散TAB模具的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分包含插入模具的腔体。 当组装两个半部时，夹具与模具建立电接触，并与老化烘箱连接。 在老化和电气测试完成之前，测试夹具不需要打开。 夹具允许在组装之前对模具进行表征。

公开(公告)号：US06372619B1

公开(公告)日：2002-04-16

申请号：US09918085

申请日：2001-07-30

申请人： Chender Huang ,  Pei-Hwa Tsao

发明人： Chender Huang ,  Pei-Hwa Tsao

IPC分类号： H01L2128

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method for fabricating a wafer level chip scale package with discrete package encapsulation and devices formed by the method are described. A dry film photoresist layer is first deposited on top of a pre-processed wafer complete with a plurality of bond pads and an I/O redistribution metal layer. The dry film photoresist layer is then patterned to form a plurality of trench openings and a plurality of via openings followed by the process of depositing a liquid photoresist material into the plurality of trench openings and plating a conductive metal into the plurality of via openings to form via plugs. After the dry film photoresist layer is removed, an encapsulant layer is printed on top of the wafer to embed the protrusions formed by the liquid photoresist material and the via plugs.

摘要翻译： 描述了利用分立封装封装制造晶片级芯片级封装的方法，以及通过该方法形成的器件。 首先将干膜光致抗蚀剂层沉积在具有多个接合焊盘和I / O再分布金属层的预处理晶片的顶部上。 然后将干膜光致抗蚀剂层图案化以形成多个沟槽开口和多个通孔开口，随后将液态光致抗蚀剂材料沉积到多个沟槽开口中并将导电金属镀覆到多个通孔开口中以形成 通过插头。 在去除干膜光致抗蚀剂层之后，将密封剂层印刷在晶片的顶部上以嵌入由液态光致抗蚀剂材料和通孔塞形成的突起。

公开(公告)号：US5302891A

公开(公告)日：1994-04-12

申请号：US973931

申请日：1992-11-10

申请人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

发明人： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  G01R31/02

CPC分类号： G01R31/2893 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H05K3/4007 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15787 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

摘要： A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

摘要翻译： 用于离散模具的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分包含插入模具的空腔。 当组装两个半部时，夹具与模具建立电接触，并与老化烘箱连接。 在老化和电气测试完成之前，测试夹具不需要打开。 夹具允许在组装之前对模具进行表征。

公开(公告)号：US5214845A

公开(公告)日：1993-06-01

申请号：US881456

申请日：1992-05-11

申请人： Jerrold L. King ,  Walter L. Moden ,  Chender Huang

发明人： Jerrold L. King ,  Walter L. Moden ,  Chender Huang

IPC分类号： H01L23/495 ,  H01L23/66

CPC分类号： H01L24/17 ,  H01L23/49524 ,  H01L23/49572 ,  H01L23/49589 ,  H01L23/66 ,  H01L24/06 ,  H01L24/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/13099 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  Y10T29/49146 ,  Y10T29/49171

摘要： This invention creates a high speed semiconductor interconnect system which contains a plurality of signal traces, each in a flexible printed circuit, and each adhesively sandwiched between or adjacent to a flexible ground circuit and a flexible power circuit. The signal, power and ground circuits are stacked in multilayers and are connected to respective lead fingers and respective die circuits by standard, known methods such as TAB or wire bond and encapsulated in a known way. The ground plane and power plane being adjacent to the signal plane reduces the power-ground loop inductance and thus reduces the package noise. By reducing the inductance, the circuit can have a shorter switching time. Also, by adding the ground plane, the power-ground capacitance is increased, which serves to reduce the effect of power supply fluctuations in the system.

摘要翻译： 本发明创建了一种高速半导体互连系统，其包含多个信号迹线，每个信号迹线在柔性印刷电路中，并且每个信号迹线粘合地夹在柔性接地电路或柔性电源电路之间或邻近柔性接地电路。 信号，电源和接地电路堆叠在多层中，并通过标准的已知方法如TAB或引线键连接到相应的引线指和相应的裸片电路，并以已知的方式封装。 与信号平面相邻的接地平面和电源平面减小了电源 - 接地环路电感，从而降低了封装噪声。 通过减小电感，电路可以具有更短的开关时间。 另外，通过添加接地层，电源接地电容增加，有助于降低系统电源波动的影响。