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公开(公告)号：US20150381218A1
公开(公告)日：2015-12-31
申请号：US14722271
申请日：2015-05-27
Applicant: QUALCOMM Incorporated
Inventor： Ying Duan , Harry Huy Dang , Chulkyu Lee
CPC classification number: H04B1/0475 , H04B3/30 , H04B15/02 , H04L25/028 , H04L25/03878
Abstract: Aspects disclosed in the detailed description include skew control for three-phase communication. A three-phase communication involves three signal branches. A signal skew may occur when one signal branch is being coupled to a common mode voltage while another signal branch is being decoupled from the common mode voltage. In this regard, in one aspect, an impedance mismatch is introduced in the signal branch being coupled to the common mode voltage to help shift a rightmost crossing of the signal skew leftward. In another aspect, a current source or a current sink is coupled to the signal branch being decoupled from the common mode voltage to help shift a leftmost crossing of the signal skew rightward. By shifting the rightmost crossing leftward and the leftmost crossing rightward, it is possible to reduce the signal skew, thus leading to reduced jitter and improved data integrity in the three-phase communication.
Abstract translation: 在详细描述中公开的方面包括用于三相通信的偏斜控制。 三相通信涉及三个信号分支。 当一个信号分支耦合到共模电压而另一个信号分支与共模电压分离时，可能发生信号偏移。 在这方面，在一个方面，在耦合到共模电压的信号支路中引入阻抗失配，以帮助向左偏移信号偏移的最右边的交叉。 在另一方面，电流源或电流吸收器耦合到信号分支与共模电压分离，以帮助向右偏移信号偏移的最左边的交叉。 通过向右移动最左边的交叉点，向右移动最左边的交叉点，可以减少信号偏移，从而导致三相通信中的抖动减小和数据完整性的改善。
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公开(公告)号：US09071220B2
公开(公告)日：2015-06-30
申请号：US13832990
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
CPC classification number: H03H2/005 , H04B1/04 , H04L25/0272 , H04L25/0278 , H04L25/14 , Y02D30/30
Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.
Abstract translation: 用于差分信号发射机的终端网络电路包括多个n个电阻元件和多个差分信号驱动器。 每个电阻元件的第一端在公共节点处耦合，其中n是整数值，并且是用于发送多个差分信号的导体的数量。 每个差分信号驱动器可以包括正极端子驱动器和负极端子驱动器。 正端子驱动器耦合到第一电阻元件的第二端，而负端子驱动器耦合到第二电阻元件的第二端。 正极端子驱动器和负极端子驱动器分别独立地切换以提供具有幅度和方向的电流。 在传输周期期间，每个电阻元件具有与其它电阻元件不同的幅度和/或方向的电流。
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公开(公告)号：US20150098538A1
公开(公告)日：2015-04-09
申请号：US14507702
申请日：2014-10-06
Applicant: QUALCOMM Incorporated
Inventor： George Alan Wiley , Chulkyu Lee
IPC: H04L7/04
CPC classification number: H04L7/042 , H04L1/205 , H04L1/206 , H04L1/247 , H04L5/20 , H04L25/0272 , H04L25/0282 , H04L25/0294 , H04L25/0298 , H04L25/4917
Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols may be generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.
Abstract translation: 描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。 信息以N相极性编码符号发送，并且可以生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。 眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。
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公开(公告)号：US20150023454A1
公开(公告)日：2015-01-22
申请号：US14336977
申请日：2014-07-21
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , George Alan Wiley , Richard Dominic Wietfeldt
IPC: H04L7/00
CPC classification number: H04L7/033 , G06F13/4295 , H04B3/50 , H04L7/00 , H04L7/0037 , H04L7/0041
Abstract: Systems and methods for multi-phase signaling are described herein. In one embodiment, a method for receiving data comprises receiving a sequence of symbols from a plurality of conductors, and generating a clock signal by detecting transitions in the received sequence of symbols. The method also comprises delaying the received sequence of symbols, and capturing one or more symbols in the delayed sequence of symbols using the clock signal, wherein a previous symbol in the delayed sequence of symbols is captured using a clock pulse in the clock signal generated based on a detected transition to a current symbol in the received sequence of symbols.
Abstract translation: 本文描述了用于多相信令的系统和方法。 在一个实施例中，一种用于接收数据的方法包括从多个导体接收符号序列，以及通过检测所接收的符号序列中的转变来产生时钟信号。 该方法还包括延迟接收到的符号序列，并使用时钟信号捕获延迟符号序列中的一个或多个符号，其中使用基于时钟信号生成的时钟信号中的时钟脉冲来捕获延迟符号序列中的先前符号 在所接收的符号序列中检测到到当前符号的转换。
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公开(公告)号：US20140003543A1
公开(公告)日：2014-01-02
申请号：US13933090
申请日：2013-07-01
Applicant: QUALCOMM Incorporated
Inventor： George A. Wiley , Glenn D. Raskin , Chulkyu Lee
IPC: H04L25/02
CPC classification number: H04L25/02 , G06F13/385 , H04L5/1423 , H04L5/16 , H04L25/0272 , H04L25/14 , H04L25/4923 , H04L25/493
Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.
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Patent Agency Ranking
公开(公告)号：US11545980B1
公开(公告)日：2023-01-03
申请号：US17469811
申请日：2021-09-08
Applicant: QUALCOMM Incorporated
Inventor： Chulkyu Lee , Jeffrey Charles Lee , George Alan Wiley
Abstract: An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.
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公开(公告)号：US10007320B2
公开(公告)日：2018-06-26
申请号：US15302767
申请日：2014-05-21
Applicant: QUALCOMM Incorporated
Inventor： Le Zhang , Wenjun Su , Chulkyu Lee
CPC classification number: G06F1/324 , G06F1/08 , G06F13/4022 , G06F13/4282 , G11C19/28 , H03M9/00 , Y02D10/14 , Y02D10/151
Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
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公开(公告)号：US09971392B2
公开(公告)日：2018-05-15
申请号：US15302767
申请日：2014-05-21
Applicant: QUALCOMM Incorporated
Inventor： Le Zhang , Wenjun Su , Chulkyu Lee
Abstract: Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.
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公开(公告)号：US09762228B2
公开(公告)日：2017-09-12
申请号：US14855238
申请日：2015-09-15
Applicant: QUALCOMM Incorporated
Inventor： Neha Agrawal , Sajin Mohamad , Chulkyu Lee
IPC: H03K21/00 , H03K7/06 , H03K19/21 , H03K3/037 , H03K21/10 , H03K23/64 , H03K23/00 , H03K21/02 , G06F1/08
CPC classification number: H03K7/06 , G06F1/08 , H03K3/037 , H03K19/21 , H03K21/00 , H03K21/026 , H03K21/10 , H03K23/00 , H03K23/64
Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.
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50.发明授权公开(公告)号：US09673969B2
公开(公告)日：2017-06-06
申请号：US14992450
申请日：2016-01-11
Applicant: QUALCOMM Incorporated
Inventor： Shoichiro Sengoku , George Alan Wiley , Chulkyu Lee , Joseph Cheung
IPC: H04L27/00 , H04L7/033 , H04L7/027 , H04L7/00 , H04L25/02 , H04L25/49 , H04L25/493 , H03K5/1252 , H03K5/1534 , H04L25/14
CPC classification number: H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0066 , H04L7/027 , H04L25/0272 , H04L25/14 , H04L25/49 , H04L25/4906 , H04L25/493
Abstract: A method for performing multi-wire signaling decoding is provided. A raw symbol spread over a plurality of n wires is received via a plurality of differential receivers. The raw symbol is converted into a sequential number from a set of sequential numbers. Each sequential number is converted to a transition number. A plurality of transition numbers is converted into a sequence of data bits. A clock signal is then extracted from the reception of raw symbols.
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