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41.发明授权Measuring leakage currents and measuring circuit for carrying out such measuring 有权测量泄漏电流和进行这种测量的测量电路公开(公告)号：US09442149B2
公开(公告)日：2016-09-13
申请号：US14326263
申请日：2014-07-08
发明人： Marco Pasotti , Fabio De Santis
IPC分类号： H01H31/12 , G01R31/02 , G01R19/165
CPC分类号： G01R31/025 , G01R19/16571
摘要： An embodiment of a measuring circuit for measuring the leakage current flowing in a portion of an electronic device when said portion is biased by a biasing unit of the electronic device is proposed. The measuring circuit includes a first section configured to generate a threshold current, a second section configured to receive the leakage current, a third section configured to compare the threshold current with the leakage current, and a fourth section configured to generate an output voltage based on the comparison between the threshold current and the leakage current. Said first section is configured to set the value of said threshold current to a different value at each reiteration of an operating cycle. Said fourth section is configured to measure said leakage current based on a detection of a change in the value of the output voltage between two reiterations of the operating cycle.
摘要翻译： 提出了一种测量电路的实施例，用于测量当电子设备的偏置单元偏压所述部分时在电子设备的一部分中流动的漏电流。 测量电路包括被配置为产生阈值电流的第一部分，被配置为接收泄漏电流的第二部分，被配置为将阈值电流与漏电流进行比较的第三部分，以及被配置为基于 阈值电流与漏电流的比较。 所述第一部分被配置为在操作周期的每次重复时将所述阈值电流的值设置为不同的值。 所述第四部分被配置为基于在操作周期的两次重复之间的输出电压的值的变化的检测来测量所述泄漏电流。
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42.发明授权公开(公告)号：US09349490B2
公开(公告)日：2016-05-24
申请号：US14597824
申请日：2015-01-15
发明人： Marcella Carissimi , Marco Pasotti
IPC分类号： G11C29/00 , G11C29/52 , G11C7/18 , G11C11/56 , G11C16/04 , G11C16/26 , G11C16/28 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1048 , G11C7/18 , G11C11/5642 , G11C16/0441 , G11C16/26 , G11C16/28 , G11C2211/4013
摘要： A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
摘要翻译： 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。
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公开(公告)号：US20240339917A1
公开(公告)日：2024-10-10
申请号：US18746752
申请日：2024-06-18
CPC分类号： H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US20230238873A1
公开(公告)日：2023-07-27
申请号：US17582431
申请日：2022-01-24
CPC分类号： H02M1/0045 , H02M3/073 , G11C13/0004
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US10139850B2
公开(公告)日：2018-11-27
申请号：US15887323
申请日：2018-02-02
发明人： Marco Pasotti , Laura Capecchi , Riccardo Zurla
摘要： A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US10109329B2
公开(公告)日：2018-10-23
申请号：US15471028
申请日：2017-03-28
摘要： A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
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公开(公告)号：US20180188763A1
公开(公告)日：2018-07-05
申请号：US15887323
申请日：2018-02-02
发明人： Marco Pasotti , Laura Capecchi , Riccardo Zurla
IPC分类号： G05F3/26
CPC分类号： G05F3/26
摘要： A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US09991000B2
公开(公告)日：2018-06-05
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US20180040380A1
公开(公告)日：2018-02-08
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US09691493B1
公开(公告)日：2017-06-27
申请号：US15244664
申请日：2016-08-23
CPC分类号： G11C16/30 , G05F3/30 , G11C5/147 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/28 , G11C2216/10 , H01L27/11521 , H01L27/1156 , H03F3/45188 , H03F3/45475 , H03F2200/456 , H03F2203/45341 , H03F2203/45342 , H03F2203/45528 , H03F2203/45674 , H03F2203/45676
摘要： A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
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