公开(公告)号：US20160308014A1

公开(公告)日：2016-10-20

申请号：US15197563

申请日：2016-06-29

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。

公开(公告)号：US09337307B2

公开(公告)日：2016-05-10

申请号：US12949696

申请日：2010-11-18

申请人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

发明人： Justin K. Brask ,  Robert S. Chau ,  Suman Datta ,  Mark L. Doczy ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Matthew V. Metz ,  Marko Radosavljevic

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66818 ,  H01L29/7834 ,  H01L29/7838 ,  H01L29/785 ,  H04B1/3827 ,  Y10S438/926

摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

公开(公告)号：US20160056374A1

公开(公告)日：2016-02-25

申请号：US14930393

申请日：2015-11-02

申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau

IPC分类号： H01L45/00 ,  G11C13/00

CPC分类号： H01L45/085 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.

摘要翻译： 描述了具有阳离子基导电氧化物元件的低电压嵌入式存储器。 例如，用于存储元件的材料层堆叠包括第一导电电极。 阳离子基导电氧化物层设置在第一导电电极上。 阳离子型导电氧化物层中具有多个阳离子空位。 第二电极设置在阳离子基导电氧化物层上。

公开(公告)号：US09224461B2

公开(公告)日：2015-12-29

申请号：US13686507

申请日：2012-11-27

申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau

IPC分类号： G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC分类号： H01L45/085 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer.

摘要翻译： 描述了具有阳离子基导电氧化物元件的低电压嵌入式存储器。 例如，用于存储元件的材料层堆叠包括第一导电电极。 阳离子基导电氧化物层设置在第一导电电极上。 阳离子型导电氧化物层中具有多个阳离子空位。 第二电极设置在阳离子基导电氧化物层上。

公开(公告)号：US20150255711A1

公开(公告)日：2015-09-10

申请号：US14723310

申请日：2015-05-27

申请人： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

发明人： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC分类号： H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

摘要翻译： 描述了具有增强的稳定性的垂直自旋转移转矩存储器（STTM）装置和制造具有增强的稳定性的垂直STTM装置的方法。 例如，用于磁隧道结的材料层堆叠包括固定磁性层。 电介质层设置在固定磁性层的上方。 自由磁性层设置在电介质层的上方。 导电氧化物材料层设置在自由磁性层上。

公开(公告)号：US20150102429A1

公开(公告)日：2015-04-16

申请号：US14576111

申请日：2014-12-18

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L29/04 ,  H01L21/308 ,  H01L29/78

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US20140170817A1

公开(公告)日：2014-06-19

申请号：US14184999

申请日：2014-02-20

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L21/02381 ,  B82Y10/00 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/31658 ,  H01L21/76283 ,  H01L21/823807 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Sil-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Sil-yGey and a covering region comprising SiO2 and enclosing the center region.

摘要翻译： 一种提供晶体管或存储单元结构的方法。 该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Sil-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Sil-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突出部。

公开(公告)号：US08581258B2

公开(公告)日：2013-11-12

申请号：US13277897

申请日：2011-10-20

申请人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

发明人： Justin K. Brask ,  Jack Kavalieros ,  Brian S. Doyle ,  Uday Shah ,  Suman Datta ,  Amlan Majumdar ,  Robert S. Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/7853 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/3085 ,  H01L21/84 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/78681 ,  H01L29/78684

摘要： A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

公开(公告)号：US08148772B2

公开(公告)日：2012-04-03

申请号：US13017309

申请日：2011-01-31

申请人： Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

发明人： Brian S. Doyle ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Robert S. Chau

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/785 ,  H01L29/66545 ,  H01L29/66795

摘要： Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

摘要翻译： 通常描述嵌入式沟道阵列晶体管（RCAT）结构和形成方法。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的第一鳍，第一鳍包括第一源极区和第一漏极区，以及形成凹陷沟道阵列晶体管（RCAT）的第一栅极结构 在设置在第一源极区域和第一漏极区域之间的第一栅极区域中，其中通过去除牺牲栅极结构以暴露第一栅极区域中的第一鳍片而形成第一栅极结构，将沟道结构凹入第一鳍片， 以及在所述凹陷通道结构上形成所述第一栅极结构。

公开(公告)号：US08129795B2

公开(公告)日：2012-03-06

申请号：US13013942

申请日：2011-01-26

申请人： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

发明人： Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Brian S. Doyle

IPC分类号： H01L21/8238

CPC分类号： H01L21/28079 ,  H01L21/26586 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845

摘要： In a metal gate replacement process, strain may be selectively induced in the channels of NMOS and PMOS transistors. For example, a material having a higher coefficient of thermal expansion than the substrate may be used to form the gate electrodes of PMOS transistors. A material with a lower coefficient of thermal expansion than that of the substrate may be used to form the gate electrodes of NMOS transistors.

摘要翻译： 在金属栅极替换工艺中，可以在NMOS和PMOS晶体管的沟道中选择性地诱发应变。 例如，可以使用具有比衬底更高的热膨胀系数的材料来形成PMOS晶体管的栅电极。 可以使用具有比基板的热膨胀系数更低的热膨胀系数的材料来形成NMOS晶体管的栅电极。