公开(公告)号：US20060041711A1

公开(公告)日：2006-02-23

申请号：US10536460

申请日：2003-11-27

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F13/00

CPC分类号： G11C11/005 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/20 ,  G11C11/4072 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/00014

摘要： A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. As data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction, the performance and the function of a mobile device can be enhanced.

摘要翻译： 提供了包括大容量ROM和RAM的存储器系统，其中启用了高速读写。 配置包括非易失性存储器（CHIP1），DRAM（CHIP3），控制电路（CHIP2）和信息处理设备（CHIP 4））的存储器系统。 FLASH中的数据提前传输到SRAM或DRAM，以加快速度。 非易失性存储器（FLASH）和DRAM（CHIP 3）之间的数据传输可以在后台执行。 包括这些多个芯片的存储器系统被配置为存储器系统模块，其中每个芯片相互层叠，并且每个芯片经由球栅阵列（BGA）和芯片之间的接合线布线。 由于FLASH中的数据可以通过将DRAM中的数据能够被复制到DRAM中并且在电源接通之后立即将数据传送到DRAM，或者通过加载指令，以与DRAM相同的速度读取DRAM的数据， 可以提高移动设备的性能和功能。

公开(公告)号：US06952368B2

公开(公告)日：2005-10-04

申请号：US10861452

申请日：2004-06-07

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F12/16 ,  G06F3/06 ,  G06F12/00 ,  G06F12/06 ,  G11C5/02 ,  G11C8/00 ,  G11C11/00 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/412 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC分类号： G06F12/0246 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/005 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40607 ,  G11C11/412 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C29/70

摘要： A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.

摘要翻译： 一种包括大容量非易失性存储器和至少一个随机存取存储器的半导体器件，所述设备的访问时间与每个随机存取存储器的访问时间相匹配。 半导体存储器件包括：具有第一读取时间的非易失性存储器FLASH; 具有比第一读取时间短100倍的第二读取时间的随机存取存储器DRAM; 电路，其包括连接到FLASH和DRAM两者的控制电路，并且能够控制对那些FLASH和DRAM的访问; 以及连接到电路的多个I / O端子。 结果，在访问DRAM之前，将FLASH数据传送到DRAM，从而与FLASH和DRAM之间的访问时间相匹配。 数据根据需要从DRAM写回到FLASH，从而保持FLASH和DRAM之间的数据匹配并存储数据。

公开(公告)号：US06847575B2

公开(公告)日：2005-01-25

申请号：US10411237

申请日：2003-04-11

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C11/41 ,  G11C5/00 ,  G11C8/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C16/04 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US06675269B2

公开(公告)日：2004-01-06

申请号：US10357412

申请日：2003-02-04

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F1200

CPC分类号： G06F13/161 ,  G06F12/0215 ,  G11C7/1018 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

摘要翻译： 存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问 在高速和低功耗下。

公开(公告)号：US06542957B2

公开(公告)日：2003-04-01

申请号：US09986348

申请日：2001-11-08

申请人： Seiji Miura ,  Kazushige Ayukawa

发明人： Seiji Miura ,  Kazushige Ayukawa

IPC分类号： G06F1200

CPC分类号： G06F13/161 ,  G06F12/0215 ,  G11C7/1018 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.

摘要翻译： 存储器控制器和数据处理器响应于连续访问不同页面的事件，将其操作模式从用于高速访问的页面模式切换到同一页面到页面关闭模式，从而执行存储器访问 在高速和低功耗下。

公开(公告)号：US06411561B1

公开(公告)日：2002-06-25

申请号：US09897503

申请日：2001-07-03

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C700

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

公开(公告)号：US07262983B2

公开(公告)日：2007-08-28

申请号：US11652012

申请日：2007-01-11

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C5/02 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US07184326B2

公开(公告)日：2007-02-27

申请号：US11268471

申请日：2005-11-08

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US06990037B2

公开(公告)日：2006-01-24

申请号：US11048915

申请日：2005-02-03

申请人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

发明人： Tomonori Sekiguchi ,  Riichiro Takemura ,  Takeshi Sakata ,  Kazushige Ayukawa ,  Takayuki Kawahara

IPC分类号： G11C8/00 ,  G11C7/02

CPC分类号： G11C7/1051 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/405 ,  G11C11/4096 ,  G11C2207/107

摘要： A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

公开(公告)号：US06404694B2

公开(公告)日：2002-06-11

申请号：US09826004

申请日：2001-04-05

申请人： Kazushige Ayukawa ,  Takao Watanabe ,  Susumu Narita

发明人： Kazushige Ayukawa ,  Takao Watanabe ,  Susumu Narita

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C8/00

摘要： A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.

摘要翻译： 存储器宏是诸如主放大器模块，每个存储器组独立的存储体模块，电源电路等功能模块的组合。存储器宏的存储容量可以容易地从大容量改变为 通过改变存储体模块的数量来实现。 存储器宏的存储体模块中的控制电路具有附加地址比较功能。 因此，可以高速访问同一页面，而无需在存储器宏之外提供任何控制电路。 此外，提供具有诸如存储器访问顺序控制的功能的模块，并且当进行存储器访问时，在输入/输出地址或数据时发出识别信息。 因此，可以通过使用ID检查数据和地址之间的一致性并控制存储器访问顺序来实现高速存储器访问，从而可以改变地址输入顺序和数据输出顺序。