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公开(公告)号：US09034716B2
公开(公告)日：2015-05-19
申请号：US13756104
申请日：2013-01-31
Inventor： Sey-Ping Sun , Sung-Li Wang , Chin-Hsiang Lin , Neng-Kuo Chen , Clement Hsingjen Wann
IPC: H01L21/336 , H01L29/40
CPC classification number: H01L29/66795 , H01L21/324 , H01L29/1054 , H01L29/401 , H01L29/66545 , H01L29/785
Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL.
Abstract translation: 通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底，衬底上的翅片，翅片侧面上的隔离区域和衬底上的伪栅极叠层，包括包裹鳍片的一部分，其被称为栅极沟道区域。 去除虚拟栅极堆叠以形成栅极沟槽，并且栅极介电层沉积在栅极沟槽中。 金属应力层（MSL）被顺应地沉积在栅极介电层上。 覆盖层沉积在MSL上。 对MSL进行热处理以实现体积膨胀。 然后去除覆盖层，并在MSL上形成金属栅极（MG）。
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公开(公告)号：US20150069913A1
公开(公告)日：2015-03-12
申请号：US14541314
申请日：2014-11-14
Inventor： Chih-Hong Hwang , Chun-Lin Chang , Nai-Han Cheng , Chi-Ming Yang , Chin-Hsiang Lin
IPC: H01J37/317
CPC classification number: H01J37/3171 , H01J3/02 , H01J3/022 , H01J3/26 , H01J37/026 , H01J37/06 , H01J2237/0041 , H01J2237/31705
Abstract: The present disclosure provides for various advantageous methods and apparatus of controlling electron emission. One of the broader forms of the present disclosure involves an electron emission element, comprising an electron emitter including an electron emission region disposed between a gate electrode and a cathode electrode. An anode is disposed above the electron emission region, and a voltage set is disposed above the anode. A first voltage applied between the gate electrode and the cathode electrode controls a quantity of electrons generated from the electron emission region. A second voltage applied to the anode extracts generated electrons. A third voltage applied to the voltage set controls a direction of electrons extracted through the anode.
Abstract translation: 本公开提供了控制电子发射的各种有利的方法和装置。 本公开的更广泛形式之一涉及电子发射元件，其包括电子发射器，其包括设置在栅电极和阴极之间的电子发射区。 阳极设置在电子发射区域的上方，并且在阳极上设置电压组。 施加在栅电极和阴极之间的第一电压控制从电子发射区产生的电子量。 施加到阳极的第二电压提取产生的电子。 施加到电压组的第三电压控制通过阳极提取的电子的方向。
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公开(公告)号：US20140213048A1
公开(公告)日：2014-07-31
申请号：US13756104
申请日：2013-01-31
Inventor： Sey-Ping Sun , Sung-Li Wang , Chin-Hsiang Lin , Neng-Kuo Chen , Clement Hsingjen Wann
IPC: H01L29/40
CPC classification number: H01L29/66795 , H01L21/324 , H01L29/1054 , H01L29/401 , H01L29/66545 , H01L29/785
Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL.
Abstract translation: 通过首先接收FinFET前体来制造FinFET器件。 FinFET前体包括衬底，衬底上的翅片，翅片侧面上的隔离区域和衬底上的虚拟栅极叠层，包括将鳍片的一部分包裹（称为栅极沟道区域）。 去除虚拟栅极堆叠以形成栅极沟槽，并且栅极介电层沉积在栅极沟槽中。 金属应力层（MSL）被顺应地沉积在栅极介电层上。 覆盖层沉积在MSL上。 对MSL进行热处理以实现体积膨胀。 然后去除覆盖层，并在MSL上形成金属栅极（MG）。
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公开(公告)号：US20140124842A1
公开(公告)日：2014-05-08
申请号：US13672258
申请日：2012-11-08
Inventor： Sung-Li Wang , Ding-Kang Shih , Chin-Hsiang Lin , Sey-Ping Sun , Clement Hsingjen Wann
IPC: H01L23/538 , H01L21/36 , H01L29/78
CPC classification number: H01L29/66636 , H01L21/02164 , H01L21/02172 , H01L21/02178 , H01L21/02186 , H01L21/02255 , H01L21/02532 , H01L21/02579 , H01L21/02614 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/30604 , H01L21/76224 , H01L21/76831 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L29/0642 , H01L29/0847 , H01L29/41758 , H01L29/41791 , H01L29/45 , H01L29/66477 , H01L29/66545 , H01L29/66628 , H01L29/66795 , H01L29/7378 , H01L29/78 , H01L29/7848 , H01L29/785 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.
Abstract translation: 本发明涉及半导体器件的接触结构。 用于半导体器件的接触结构的示例性结构包括：基底，其包括主表面和主表面下方的沟槽; 填充沟槽的应变材料，其中应变材料的晶格常数不同于衬底的晶格常数; 在所述应变材料上具有开口的层间介电层（ILD）层，其中所述开口包括电介质侧壁和应变材料底部; 在开口的侧壁和底部上的半导体层; 半导体层上的介电层; 以及填充介电层的开口的金属层。
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公开(公告)号：US12300507B2
公开(公告)日：2025-05-13
申请号：US18438047
申请日：2024-02-09
Inventor： Yen-Hao Chen , Wei-Han Lai , Ching-Yu Chang , Chin-Hsiang Lin
IPC: H01L21/00 , H01L21/02 , H01L21/027 , H01L21/3105 , H01L21/321
Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
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Patent Agency Ranking
公开(公告)号：US20240345472A1
公开(公告)日：2024-10-17
申请号：US18751858
申请日：2024-06-24
Inventor： Hsin-Chang Lee , Pei-Cheng Hsu , Ta-Cheng Lien , Li-Jui Chen , Tsai-Sheng Gau , Chin-Hsiang Lin
IPC: G03F1/64 , H01L21/033
CPC classification number: G03F1/64 , H01L21/0337
Abstract: A method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. The pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. Compressive pressure can be applied to reduce the thickness of the initial membrane(s). Alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. A mounting frame is then affixed to a portion of the extended membrane. The mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. The resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. The pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.
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公开(公告)号：US11935757B2
公开(公告)日：2024-03-19
申请号：US18132868
申请日：2023-04-10
Inventor： Yen-Hao Chen , Wei-Han Lai , Ching-Yu Chang , Chin-Hsiang Lin
IPC: H01L21/00 , H01L21/02 , H01L21/027 , H01L21/3105 , H01L21/321
CPC classification number: H01L21/32115 , H01L21/02118 , H01L21/02406 , H01L21/02557 , H01L21/0276 , H01L21/31058
Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
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公开(公告)号：US20230384679A1
公开(公告)日：2023-11-30
申请号：US18232717
申请日：2023-08-10
Inventor： An-Ren ZI , Chin-Hsiang Lin , Ching-Yu Chang
IPC: G03F7/11 , G03F7/004 , G03F7/038 , G03F7/039 , G03F7/16 , G03F7/20 , G03F7/32 , G03F7/38 , H01L21/027
CPC classification number: G03F7/11 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/168 , G03F7/2002 , G03F7/32 , G03F7/38 , H01L21/0274
Abstract: A method of manufacturing a semiconductor device includes forming a photoresist under-layer including a photoresist under-layer composition over a semiconductor substrate, and forming a photoresist layer including a photoresist composition over the photoresist under-layer. The photoresist layer is selectively exposed to actinic radiation and the photoresist layer is developed to form a pattern in the photoresist layer. The photoresist under-layer composition includes a polymer having pendant acid-labile groups, a polymer having crosslinking groups or a polymer having pendant carboxylic acid groups, an acid generator, and a solvent. The photoresist composition includes a polymer, a photoactive compound, and a solvent.
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49.发明授权公开(公告)号：US11709435B2
公开(公告)日：2023-07-25
申请号：US17733664
申请日：2022-04-29
Inventor： Shinn-Sheng Yu , Ru-Gun Liu , Hsu-Ting Huang , Kenji Yamazoe , Minfeng Chen , Shuo-Yen Chou , Chin-Hsiang Lin
CPC classification number: G03F7/70641 , G03F7/2004 , G03F7/2022 , G03F7/70558
Abstract: A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.
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公开(公告)号：US11626293B2
公开(公告)日：2023-04-11
申请号：US17712982
申请日：2022-04-04
Inventor： Yen-Hao Chen , Wei-Han Lai , Ching-Yu Chang , Chin-Hsiang Lin
IPC: H01L21/00 , H01L21/321 , H01L21/02 , H01L21/027 , H01L21/3105
Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
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