公开(公告)号：US20170309549A1

公开(公告)日：2017-10-26

申请号：US15135318

申请日：2016-04-21

Applicant: Texas Instruments Incorporated

Inventor： Kurt Peter Wachtler ,  Seunghyun Chae ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/60

CPC classification number: H01L23/49503 ,  H01L23/49541 ,  H01L23/49572 ,  H01L23/5383 ,  H01L2021/60022 ,  H01L2224/16245 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An integrated circuit die may be fabricating to have a plurality of contacts. A metal post may be formed on each of the plurality of contacts. A plurality of bumps may be formed on a plurality of contact regions of a leadframe or on the posts, in which the plurality of bumps are formed with a material that includes metal nanoparticles. The IC die may be attached to the leadframe by aligning the metal posts to the leadframe and sintering the metal nanoparticles in the plurality of bumps to form a sintered metal bond between each metal post and corresponding contact region of the leadframe.

公开(公告)号：US09679864B2

公开(公告)日：2017-06-13

申请号：US15293075

申请日：2016-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Matthew David Romig ,  Steven Alfred Kummerl ,  Wei-Yan Shih

IPC: H01L21/44 ,  H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L21/48 ,  H01L23/552 ,  H01L23/538 ,  H01L23/66

CPC classification number: H01L24/27 ,  H01L21/4867 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L2223/6627 ,  H01L2224/24998 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29026 ,  H01L2224/29076 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

公开(公告)号：US20170033072A1

公开(公告)日：2017-02-02

申请号：US15293075

申请日：2016-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Juan Alejandro Herbsommer ,  Matthew David Romig ,  Steven Alfred Kummerl ,  Wei-Yan Shih

IPC: H01L23/00 ,  H01L23/66

CPC classification number: H01L24/27 ,  H01L21/4867 ,  H01L21/76838 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L2223/6627 ,  H01L2224/24998 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29026 ,  H01L2224/29076 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

Abstract translation: 一种形成封装半导体器件的方法包括提供一种第一半导体管芯（第一管芯），其上具有接合焊盘，其面朝上安装在封装衬底上或引线框架（衬底）的管芯焊盘上，其中衬底包括端子或接触焊盘 （基板焊盘）。 形成第一电介质层，包括印刷第一电介质前体层，该第一电介质前体层包括具有从衬底焊盘延伸到接合焊盘的第一液体载体溶剂的第一油墨。 印刷第一互连前体层，其包括在从衬底焊盘延伸到接合焊盘的第一介电层上方具有第二液体载体的第二油墨。 烧结或固化第一互连前体层至少去除第二液体载体以形成包括将各个衬底焊盘连接到各个焊盘的墨残余物的导电互连。

公开(公告)号：US20240312862A1

公开(公告)日：2024-09-19

申请号：US18674006

申请日：2024-05-24

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/74 ,  H01L21/768 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit includes a semiconductor substrate. The integrated circuit also includes a trench in the semiconductor substrate, the trench including a layer of a nanoparticle material. The integrated circuit further includes an interconnect region above the trench.

公开(公告)号：US12080633B2

公开(公告)日：2024-09-03

申请号：US16123100

申请日：2018-09-06

Applicant: Texas Instruments Incorporated

Inventor： Jo Bito ,  Benjamin Stassen Cook ,  Steven Kummerl

IPC: H01L23/495 ,  H01L23/498

CPC classification number: H01L23/49541 ,  H01L23/4951 ,  H01L23/49537 ,  H01L23/49816

Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.

公开(公告)号：US11996343B2

公开(公告)日：2024-05-28

申请号：US17114219

申请日：2020-12-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/34 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/768 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L21/74

CPC classification number: H01L23/367 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L27/0248 ,  H01L21/743 ,  H01L23/3677 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

公开(公告)号：US11865773B2

公开(公告)日：2024-01-09

申请号：US16680153

申请日：2019-11-11

Applicant: Texas Instruments Incorporated

Inventor： Daniel Lee Revier ,  Sean Ping Chang ,  Benjamin Stassen Cook

IPC: B29C64/165 ,  B33Y80/00 ,  B33Y10/00 ,  B33Y70/00 ,  B33Y30/00 ,  B28B1/00 ,  H01L21/02 ,  H01L21/288 ,  H01L21/67 ,  B22F10/00 ,  B22F10/14 ,  B22F12/37 ,  B22F12/53 ,  B22F12/55 ,  B22F12/57 ,  B22F12/41 ,  B29L31/34 ,  B22F12/00 ,  B22F12/49

CPC classification number: B29C64/165 ,  B22F10/00 ,  B22F10/14 ,  B22F12/37 ,  B22F12/53 ,  B22F12/55 ,  B22F12/57 ,  B28B1/001 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02288 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02623 ,  H01L21/288 ,  H01L21/6715 ,  B22F12/226 ,  B22F12/41 ,  B22F12/49 ,  B29L2031/34 ,  B22F2999/00 ,  B22F10/30 ,  B22F12/55 ,  B22F12/57

Abstract: A layer of additive material is formed in a circular printing area on a substrate using additive sources distributed across a printing zone. The additive sources form predetermined discrete amounts of the additive material. The substrate and the additive sources are rotated with respect to each other around a center of rotation, so that a pattern of the additive material is formed in a circular printing area on the substrate. Each additive source receives actuation waveforms at an actuation frequency that is proportional to a distance of the additive source from the center of rotation. The actuation waveforms include formation signals, with a maximum of one formation signal in each cycle of the actuation frequency. The formation signals result in the additive sources forming the predetermined discrete amounts of the additive material on the substrate.

公开(公告)号：US20230243770A1

公开(公告)日：2023-08-03

申请号：US18180572

申请日：2023-03-08

Applicant: Texas Instruments Incorporated

Inventor： Archana VENUGOPAL ,  Benjamin Stassen Cook ,  Nazila Dadvand ,  Luigi Colombo

IPC: G01N27/12 ,  G01N33/00 ,  H01L29/06 ,  H01L29/16 ,  C23C16/04 ,  C23C18/06 ,  C23C18/16 ,  C23C16/26 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: G01N27/127 ,  G01N33/0027 ,  G01N27/128 ,  H01L29/0669 ,  H01L29/1606 ,  C23C16/042 ,  C23C16/04 ,  C23C18/06 ,  C23C18/1605 ,  C23C18/1603 ,  C23C16/047 ,  C23C18/1607 ,  C23C18/1657 ,  C23C16/26 ,  C23C18/1648 ,  B33Y10/00 ,  B33Y80/00 ,  H01L21/02606

Abstract: A gas sensor has a microstructure sensing element which comprises a plurality of interconnected units wherein the units are formed of connected graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US11676930B2

公开(公告)日：2023-06-13

申请号：US17315102

申请日：2021-05-07

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier ,  Sadia Naseem ,  Mahmud Halim Chowdhury

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L24/83 ,  H01L2224/32058 ,  H01L2924/35121

Abstract: In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

公开(公告)号：US11545466B2

公开(公告)日：2023-01-03

申请号：US17150825

申请日：2021-01-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Bichoy Bahr ,  Baher Haroun

IPC: H01L25/065 ,  H01L21/673 ,  H03B5/08 ,  H01F38/14

Abstract: A multi-die module includes a first die with a first electronic device and a second die with a second electronic device. The multi-die module also includes a contactless coupler configured to convey signals between the first electronic device and the second electronic device. The multi-die module also includes a coupling loss reduction structure.