公开(公告)号：US10157770B2

公开(公告)日：2018-12-18

申请号：US15660107

申请日：2017-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/70 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.

公开(公告)号：US09679980B2

公开(公告)日：2017-06-13

申请号：US14208905

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  I-Ting Li ,  Ming-Hsiang Kao

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11521 ,  G11C16/04

CPC classification number: H01L29/42328 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

公开(公告)号：US09589804B2

公开(公告)日：2017-03-07

申请号：US14814370

申请日：2015-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Shiu-Ko Jangjian ,  Chung-Ren Sun ,  Ming-Te Chen ,  Ting-Chun Wang ,  Jun-Jie Cheng

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The lining oxide layer peripherally encloses the second side surface of the semiconductor fin. The silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface.

Abstract translation: 半导体器件包括半导体鳍片，衬里氧化物层，氮化硅基层和栅极氧化物层。 半导体翅片具有顶表面，与顶表面相邻的第一侧表面，以及设置在第一侧表面下方并与其邻近的第二侧表面。 衬里氧化物层周边地包围半导体鳍片的第二侧表面。 氮化硅基层与衬里氧化物层一致地设置。 栅极氧化物层与顶表面和第一侧表面共形设置。

公开(公告)号：US20160111511A1

公开(公告)日：2016-04-21

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09245974B2

公开(公告)日：2016-01-26

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09099324B2

公开(公告)日：2015-08-04

申请号：US14062838

申请日：2013-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离位于半导体衬底中，并且包括外延层和电介质材料。 外延层位于半导体的沟槽中并由其周边封闭，其中通过进行蚀刻和外延工艺形成外延层。 蚀刻和外延工艺包括蚀刻沟槽的侧壁的一部分和沟槽的底表面的一部分，并且形成与侧壁的剩余部分和底表面的剩余部分共形的外延层。 电介质材料由外延层周边封闭。

公开(公告)号：US09040385B2

公开(公告)日：2015-05-26

申请号：US13949756

申请日：2013-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Hui Huang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Xiao-Meng Chen

IPC: H01L21/30 ,  H01L21/02 ,  H01L21/768 ,  H01L21/18 ,  H01L21/67 ,  H01L33/00

CPC classification number: H01L21/67207 ,  H01L21/02041 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/02334 ,  H01L21/187 ,  H01L21/67017 ,  H01L21/67196 ,  H01L21/68707 ,  H01L33/0079 ,  Y10S438/906

Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.

Abstract translation: 提供了用于清洁用于混合键合的半导体晶片的表面的机构的实施例。 用于清洁用于混合键合的半导体晶片的表面的方法包括提供半导体晶片，并且半导体晶片具有嵌入绝缘层中的导电焊盘。 该方法还包括对半导体晶片的表面进行等离子体处理，并且在导电结构的表面上形成金属氧化物。 该方法还包括使用清洁溶液进行清洁处理以与金属氧化物进行还原反应，使得在导电结构的表面上形成金属 - 氢键。 该方法还包括将半导体晶片在真空下转移到接合室用于混合键合。 还提供了用于混合键合和集成系统的机构的实施例。

公开(公告)号：US20150031189A1

公开(公告)日：2015-01-29

申请号：US13949756

申请日：2013-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Hui Huang ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Chia-Shiung Tsai ,  Xiao-Meng Chen

IPC: H01L21/02 ,  H01L21/18 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/67207 ,  H01L21/02041 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/02334 ,  H01L21/187 ,  H01L21/67017 ,  H01L21/67196 ,  H01L21/68707 ,  H01L33/0079 ,  Y10S438/906

Abstract: Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided.

Abstract translation: 提供了用于清洁用于混合键合的半导体晶片的表面的机构的实施例。 用于清洁用于混合键合的半导体晶片的表面的方法包括提供半导体晶片，并且半导体晶片具有嵌入绝缘层中的导电焊盘。 该方法还包括对半导体晶片的表面进行等离子体处理，并且在导电结构的表面上形成金属氧化物。 该方法还包括使用清洁溶液进行清洁处理以与金属氧化物进行还原反应，使得在导电结构的表面上形成金属 - 氢键。 该方法还包括将半导体晶片在真空下转移到接合室用于混合键合。 还提供了用于混合键合和集成系统的机构的实施例。

公开(公告)号：US11955496B2

公开(公告)日：2024-04-09

申请号：US17036202

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

公开(公告)号：US11923235B2

公开(公告)日：2024-03-05

申请号：US17877824

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Chii-Ming Wu ,  Sen-Hong Syue ,  Cheng-Po Chau

IPC: H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/105 ,  H01L27/146

CPC classification number: H01L21/76229 ,  H01L21/76232 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/785 ,  H01L27/105 ,  H01L27/1463

Abstract: A method includes forming a first trench and a second trench in a semiconductor substrate; forming a first mask over the semiconductor substrate, wherein the first mask is disposed in a first portion of the first trench and exposes the second trench and a second portion of the first trench; after forming the first mask, deepening the second trench and the second portion of the first trench; after deepening the second trench and the second portion of the first trench, removing the first mask; and after removing the first mask, filling a dielectric material in both the first and second trenches.