公开(公告)号：US11810831B2

公开(公告)日：2023-11-07

申请号：US17872488

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/18 ,  H01L21/822 ,  H01L25/11

CPC classification number: H01L23/3135 ,  H01L21/56 ,  H01L23/18 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/563 ,  H01L21/568 ,  H01L21/8221 ,  H01L25/117 ,  H01L2225/06513

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

公开(公告)号：US20230317552A1

公开(公告)日：2023-10-05

申请号：US18328387

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Chen ,  Hung-Yu Chen ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/04 ,  H01L23/31 ,  H01L23/40

CPC classification number: H01L23/3737 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/4006 ,  H01L2023/4087

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

公开(公告)号：US20230230882A1

公开(公告)日：2023-07-20

申请号：US17721109

申请日：2022-04-14

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Yi-Chao Mao ,  Tsung-Fu Tsai ,  Szu-Wei Lu ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/02076 ,  H01L21/6836 ,  H01L23/544 ,  H01L24/08 ,  H01L24/80 ,  H01L2221/68327 ,  H01L2223/5446 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments provide a precutting technique to cut parallel openings at a front surface of a device wafer, then flipping the device wafer over and completing the cut from the back side of the device wafer to singulate a die from the wafer. The precutting technique and back side cutting technique combined provides an indentation in the side surface(s) of the device.

公开(公告)号：US20230092361A1

公开(公告)日：2023-03-23

申请号：US17994548

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Kung-Chen Yeh ,  Li-Chung Kuo ,  Pu Wang ,  Szu-Wei Lu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H01L21/78

Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

公开(公告)号：US11600595B2

公开(公告)日：2023-03-07

申请号：US16936433

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ching Shih ,  Chih-Wei Wu ,  Szu-Wei Lu

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant. The top metal layers, the bottom metal layers, and the intermetallic layers are in contact with the first encapsulant.

公开(公告)号：US20230052821A1

公开(公告)日：2023-02-16

申请号：US17980914

申请日：2022-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Pan ,  Li-Hui Cheng ,  Chin-Fu Kao ,  Szu-Wei Lu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/306 ,  H01L21/304 ,  H01L21/78 ,  H01L21/56 ,  H01L25/065

Abstract: In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.

公开(公告)号：US11527454B2

公开(公告)日：2022-12-13

申请号：US17362185

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US20220375814A1

公开(公告)日：2022-11-24

申请号：US17883348

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

Abstract: 3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.

公开(公告)号：US20220359355A1

公开(公告)日：2022-11-10

申请号：US17870099

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20220359339A1

公开(公告)日：2022-11-10

申请号：US17381952

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Hsieh ,  Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/498 ,  H01L23/373 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.