公开(公告)号：US20240085621A1

公开(公告)日：2024-03-14

申请号：US18151033

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Chih-Wei Tseng ,  Jui Lin Chao

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12121

Abstract: A method includes encapsulating a first device die and a second device die in an encapsulant, and forming an interconnect structure over and electrically connecting to the first device die and the second device die. A waveguide is formed in the interconnect structure. An optical-engine based interconnect component is bonded to the interconnect structure. The optical-engine based interconnect component forms a part of a signal path that connects the first device die to the second device die.

公开(公告)号：US20240077669A1

公开(公告)日：2024-03-07

申请号：US18111290

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Jiun Yi Wu ,  Szu-Wei Lu

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/42

CPC classification number: G02B6/12004 ,  G02B6/262 ,  G02B6/4239 ,  G02B2006/12102 ,  G02B2006/12104

Abstract: An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

公开(公告)号：US11923207B2

公开(公告)日：2024-03-05

申请号：US18308909

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/49 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/49822 ,  H01L24/13 ,  H01L21/568 ,  H01L2221/68331 ,  H01L2224/10122 ,  H01L2924/19106

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

公开(公告)号：US11894318B2

公开(公告)日：2024-02-06

申请号：US17097206

申请日：2020-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121

Abstract: A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

公开(公告)号：US20240038669A1

公开(公告)日：2024-02-01

申请号：US18355824

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chieh-Yen Chen ,  Chuei-Tang Wang ,  Chung-Hao Tsai

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/818 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

Abstract: A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.

公开(公告)号：US20240006270A1

公开(公告)日：2024-01-04

申请号：US17856689

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yi Kuo ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Cheng-Chieh Hsieh ,  Chung-Ju Lee ,  Szu-Wei Lu

IPC: H01L23/473 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/473 ,  H01L23/3135 ,  H01L25/18 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/94

Abstract: In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

公开(公告)号：US11862606B2

公开(公告)日：2024-01-02

申请号：US17361791

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/50 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81385 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.

公开(公告)号：US11862605B2

公开(公告)日：2024-01-02

申请号：US17140860

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

公开(公告)号：US11856800B2

公开(公告)日：2023-12-26

申请号：US16806470

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H10B99/00 ,  H01L27/146 ,  H01L21/56

CPC classification number: H10B99/00 ,  H01L27/14618 ,  H01L21/56

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

公开(公告)号：US11854994B2

公开(公告)日：2023-12-26

申请号：US17815660

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Ming Shih Yeh

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A redistribution structure for a semiconductor device and a method of forming the same are provided. The semiconductor device includes a die encapsulated by an encapsulant, the die including a pad, and a connector electrically connected to the pad. The semiconductor device further includes a first via in physical contact with the connector. The first via is laterally offset from the connector by a first non-zero distance in a first direction. The first via has a tapered sidewall.