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公开(公告)号：US20170221858A1
公开(公告)日：2017-08-03
申请号：US15488933
申请日：2017-04-17
发明人： Chen-Hua Yu , Shang-Yun Hou , Yun-Han Lee
IPC分类号： H01L23/00 , H01L25/065 , G05F3/02 , H01L23/28 , H01L27/28 , H01L25/10 , H01L27/06 , H01L27/12 , H01L27/24 , H01L49/02 , H01L23/522
CPC分类号： H01L24/97 , G05F3/02 , H01L21/4846 , H01L23/28 , H01L23/481 , H01L23/5226 , H01L23/5227 , H01L23/5389 , H01L24/25 , H01L25/0652 , H01L25/105 , H01L27/0688 , H01L27/124 , H01L27/2481 , H01L27/283 , H01L28/10 , H01L2224/16225 , H01L2225/0651 , H01L2225/06541 , H01L2225/06582 , H01L2225/1041 , H01L2225/1058 , H01L2225/107
摘要： A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
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公开(公告)号：US09647028B2
公开(公告)日：2017-05-09
申请号：US15194961
申请日：2016-06-28
发明人： Sandeep Kumar Goel , Yun-Han Lee
CPC分类号： H01L27/14687 , H01L21/78 , H01L25/50 , H01L27/14609 , H01L27/14632 , H01L27/14634 , H01L27/1469 , H04N5/367 , H04N5/378
摘要： A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.
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公开(公告)号：US09391110B2
公开(公告)日：2016-07-12
申请号：US14458873
申请日：2014-08-13
发明人： Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： H01L23/02 , H01L27/146 , H01L21/78
CPC分类号： H01L27/14687 , H01L21/78 , H01L25/50 , H01L27/14609 , H01L27/14632 , H01L27/14634 , H01L27/1469 , H04N5/367 , H04N5/378
摘要： A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type.
摘要翻译： 晶片（WOW）堆叠上的晶片包括具有第一类型的管芯的第一晶片。 WOW堆叠还包括结合到第一晶片的第二晶片。 第二晶片具有第二类型的管芯。 第二类型的模具的整数数目与第一类型的相应的模具结合。 结合到第一类型的相应管芯的第二类型的管芯的总面积小于或等于第一类型的相应管芯的面积。 第一类型的管芯的功能与第二类型的管芯的功能不同。
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公开(公告)号：US20150289376A1
公开(公告)日：2015-10-08
申请号：US14745673
申请日：2015-06-22
发明人： Yun-Han Lee , Mark Shane Peng , Shyh-An Chi
CPC分类号： H05K1/181 , H01L23/147 , H01L23/538 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2223/6677 , H01L2224/16225 , H01L2224/16235 , H01L2225/06565 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H05K1/111 , H05K1/115 , H05K1/141 , H05K2201/10045 , H05K2201/10053 , H05K2201/10378 , H01L2924/00
摘要： A package structure includes a networking unit including a plurality of switches/routers and a plurality of network interface units coupled to the plurality of switches/routers, and an interposer including a plurality of metal connections. The interposer is substantially free from functional elements built therein. A functional element is outside of, and bonded onto, the interposer, wherein the functional element is electrically coupled to the networking unit through the plurality of metal connections.
摘要翻译： 一种包装结构包括一个包括多个交换机/路由器的联网单元和耦合到该多个交换机/路由器的多个网络接口单元，以及包括多个金属连接的插件。 内插器基本上没有内置的功能元件。 功能元件在插入器之外并且结合到插入器上，其中功能元件通过多个金属连接电耦合到联网单元。
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公开(公告)号：US20150213183A1
公开(公告)日：2015-07-30
申请号：US14679843
申请日：2015-04-06
发明人： Yun-Han Lee , Wu-An Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
摘要翻译： 公开了一种用于设计集成电路的系统和方法。 一个实施例包括将具有第一单元高度的标准单元放置到具有不同高度的单元行中。 标准单元可以具有小于单元行的高度，或者可以具有大于单元行的高度。 使用垂直填料和水平填料将标准池延伸并连接到相邻的单元，而不必重新设计整个单元行。
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公开(公告)号：US20140115553A1
公开(公告)日：2014-04-24
申请号：US14139436
申请日：2013-12-23
发明人： Yun-Han Lee , Wu-An Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
摘要翻译： 公开了一种用于设计集成电路的系统和方法。 一个实施例包括将具有第一单元高度的标准单元放置到具有不同高度的单元行中。 标准单元可以具有小于单元行的高度，或者可以具有大于单元行的高度。 使用垂直填料和水平填料将标准池延伸并连接到相邻的单元，而不必重新设计整个单元行。
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公开(公告)号：US20140015599A1
公开(公告)日：2014-01-16
申请号：US14025171
申请日：2013-09-12
发明人： Shyh-An Chi , Shiue Tsong Shen , Jyy Anne Lee , Yun-Han Lee
IPC分类号： G05F3/20
CPC分类号： G05F3/205 , H03K19/00384
摘要： An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.
摘要翻译： 集成电路包括响应于PVT效应的过程电压温度（PVT）效应传感器，耦合到PVT效应传感器并被配置为量化PVT效应以提供输出的PVT效应量化器，以及配置成接收输出的偏置控制器 的PVT效应量化器，并为NMOS或PMOS晶体管的衬底提供偏置电压。 偏置控制器被配置为将从PVT效应量化器接收的输出与阈值进行比较，并且根据输出是高于还是低于阈值来降低或增加偏置电压。
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公开(公告)号：US12093176B2
公开(公告)日：2024-09-17
申请号：US18341088
申请日：2023-06-26
IPC分类号： G06F12/0891 , G06F12/0804 , G11C5/02 , G11C5/04 , G11C7/22
CPC分类号： G06F12/0804 , G06F12/0891 , G11C5/025 , G11C5/04 , G11C7/22 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608 , H01L2224/16225 , H01L2924/15311
摘要： A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
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公开(公告)号：US20240071941A1
公开(公告)日：2024-02-29
申请号：US17897648
申请日：2022-08-29
发明人： Ming-Fa Chen , Yun-Han Lee , Lee-Chung Lu
IPC分类号： H01L23/538 , H01L21/48 , H01L23/00 , H01L25/065 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/5386 , H01L21/486 , H01L24/08 , H01L24/80 , H01L25/0655 , H01L29/0673 , H01L29/401 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , H01L23/5385 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896 , H01L2924/13081
摘要： A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed on an opposite side from the first and second device features with respect to the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.
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公开(公告)号：US20230333981A1
公开(公告)日：2023-10-19
申请号：US18341088
申请日：2023-06-26
IPC分类号： G06F12/0804 , G11C5/04 , G11C5/02 , G06F12/0891 , G11C7/22
CPC分类号： G06F12/0804 , G11C5/04 , G11C5/025 , G06F12/0891 , G11C7/22 , H01L2224/16225 , H01L2924/15311 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608
摘要： A memory system includes multiple groups of primary memory cells residing in a first die or a stack of first dies, multiple groups of cache memory cells residing in a second die, an interposer, and control circuits residing in a third die. Each group of the cache memory cells is associated with a corresponding group of the primary memory cells. The first die or the stack of first dies is coupled to a top surface of the second die through a first group of bumps. A bottom surface of the second die is coupled to a top surface of the interposer through a second group of bumps. The control circuits are associated with the primary memory cells and the cache memory cells. The third die is positioned aside the second die and coupled to the top surface of the interposer through a third group of pumps.
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