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41.发明申请METHOD FOR FABRICATING CHIP SCALE PACKAGE STRUCTURE WITH METAL PADS EXPOSED FROM AN ENCAPSULANT 有权用于从包裹体渗出的金属垫制造芯片尺寸包装结构的方法公开(公告)号：US20100233855A1
公开(公告)日：2010-09-16
申请号：US12788772
申请日：2010-05-27
申请人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/56
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3114 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/20 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： A chip scale package structure and a method for fabricating the same are disclosed. The method includes forming metal pads on a predetermined part of a carrier; mounting chips on the carrier, each of the chips having a plurality of conductive bumps soldered to the metal pads; forming an encapsulant on the carrier to encapsulate the chips and the conductive bumps; removing the carrier to expose the metal pads and even the metal pads with a surface of the encapsulant; forming on the encapsulant a plurality of first conductive traces electrically connected to the metal pads; applying a solder mask on the first conductive traces, and forming a plurality of openings on the solder mask to expose a predetermined part of the first conductive traces; forming a plurality of conductive elements on the predetermined part; and cutting the encapsulant to form a plurality of chip scale package structures.
摘要翻译： 公开了一种芯片级封装结构及其制造方法。 该方法包括在载体的预定部分上形成金属垫; 在载体上安装芯片，每个芯片具有焊接到金属焊盘的多个导电凸块; 在载体上形成密封剂以封装芯片和导电凸块; 移除载体以暴露金属垫和甚至具有密封剂表面的金属垫; 在所述密封剂上形成电连接到所述金属焊盘的多个第一导电迹线; 在所述第一导电迹线上施加焊接掩模，以及在所述焊接掩模上形成多个开口以暴露所述第一导电迹线的预定部分; 在所述预定部分上形成多个导电元件; 以及切割所述密封剂以形成多个芯片级封装结构。
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公开(公告)号：US07638879B2
公开(公告)日：2009-12-29
申请号：US11985662
申请日：2007-11-16
申请人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Yih-Jenn Jiang , Han-Ping Pu , Chien-Ping Huang , Cheng-Hsu Hsiao
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/6835 , H01L24/48 , H01L24/97 , H01L2221/68345 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15747 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer. In the present invention, the distance between the semiconductor package and the external device is increased, and thermal stress caused by difference between the thermal expansion coefficients is reduced, so as to enhance the reliability of the product.
摘要翻译： 公开了半导体封装和制造方法。 制造方法包括在金属载体的一个表面上施加牺牲层，在牺牲层上施加绝缘层，以及在牺牲层和绝缘层中形成通孔以露出金属载体; 在每个通孔中形成导电金属层; 在所述绝缘层上形成图案化电路层，以电连接到所述导电金属层; 将至少一个芯片安装在所述绝缘层上并将所述芯片电连接到所述图案化电路层; 形成密封剂以封装所述芯片和所述图案化电路层; 并且去除金属载体和牺牲层以暴露绝缘层和导电金属层，以允许导电金属层从绝缘层突出。 在本发明中，半导体封装和外部器件之间的距离增加，由于热膨胀系数之差导致的热应力降低，从而提高了产品的可靠性。
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公开(公告)号：US20090261476A1
公开(公告)日：2009-10-22
申请号：US12148319
申请日：2008-04-18
IPC分类号： H01L23/482 , H01L21/60
CPC分类号： H01L24/19 , H01L21/6835 , H01L23/3114 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2221/68345 , H01L2224/24226 , H01L2224/82001 , H01L2225/1035 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311
摘要： A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.
摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括以下步骤：提供具有布置在其上的导电电路的载体板和具有设置在其上的焊料焊盘的有源表面的多个芯片，其中导电凸块设置在焊盘上; 将芯片安装在载板上; 用电介质层填充芯片之间的间隔，并在每个芯片周边的电介质层中形成开口以露出导电电路; 在所述电介质层的开口部和所述芯片的有源面的外围形成金属层，用于电连接所述导电凸块和所述导电电路; 并沿着芯片之间的电介质层切割并去除载体板以分离每个芯片并使导电电路与非活性表面相接触。
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44.发明授权Method for fabricating wafer level semiconductor package with build-up layer 有权用于制造具有堆积层的晶片级半导体封装的方法公开(公告)号：US07445957B2
公开(公告)日：2008-11-04
申请号：US11580560
申请日：2006-10-12
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。
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45.发明申请公开(公告)号：US20080213942A1
公开(公告)日：2008-09-04
申请号：US12074321
申请日：2008-03-03
CPC分类号： H01L23/3128 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L24/16 , H01L2224/13099 , H01L2224/16 , H01L2224/73203 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs.
摘要翻译： 本发明提供一种用于制造应用于其中的半导体器件和载体的方法。 该方法包括以下步骤：将芯片安装的基板设置在载体的开口中; 在所述载体中至少形成存储孔径和至少一个检查孔; 将粘合剂注入到存储孔中，以通过毛细管力用粘合剂填充基底和载体之间的间隙; 确定检查孔是否填充有粘合剂以确定间隙是否完全被粘合剂填充; 响应于积极的结果，进行成型处理以形成用于封装芯片的模塑料; 并且执行焊球的注入和单一化处理以形成具有所需尺寸的半导体器件。 检查孔径用肉眼检查以确定间隙是否完全充满粘合剂，从而降低检查成本并提高产品的产量，而不需要额外的包装成本。
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46.发明申请公开(公告)号：US20080017977A1
公开(公告)日：2008-01-24
申请号：US11801625
申请日：2007-05-10
申请人： Wen-Tsung Tseng , Chien-Ping Huang , Ho-Yi Tsai , Cheng-Hsu Hsiao
发明人： Wen-Tsung Tseng , Chien-Ping Huang , Ho-Yi Tsai , Cheng-Hsu Hsiao
IPC分类号： H01L23/34
CPC分类号： H01L23/4334 , H01L24/48 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat dissipating semiconductor package and a heat dissipating structure thereof are provided. The heat dissipating structure includes an outer surface, consecutive recessed step portions, and a pressure-releasing groove. The outer surface is exposed from an encapsulant made of a molding compound. The step portions are formed at an edge of the outer surface and have decreasing depths wherein the closer a step portion to a central position of the outer surface, the smaller the depth of this step portion is. The pressure-releasing groove is disposed next to and deeper than the innermost one of the step portions. A molding compound flows to the step portions and absorbs heat from an encapsulation mold quickly, such that a flowing speed of the molding compound is reduced. Pressure suffered by air remaining at the step portions is released through the pressure-releasing groove, thereby preventing flashes of the molding compound and resin bleeding.
摘要翻译： 提供散热半导体封装及其散热结构。 散热结构包括外表面，连续凹进的台阶部分和压力释放槽。 外表面从由模塑料制成的密封剂暴露。 台阶部分形成在外表面的边缘处并且具有减小的深度，其中台阶部分越接近外表面的中心位置，该阶梯部分的深度越小。 压力释放槽设置在步骤部分的最内侧之上并深度。 模塑料流到台阶部分并迅速从封装模具吸收热量，从而降低模塑料的流动速度。 通过压力释放槽释放在台阶部分残留的空气所产生的压力，从而防止模塑料的闪烁和树脂渗色。
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公开(公告)号：USRE39957E1
公开(公告)日：2007-12-25
申请号：US10934632
申请日：2004-09-03
申请人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Tzong-Da Ho , Cheng-Hsu Hsiao
IPC分类号： H01C21/66 , H01C21/00 , H01L21/44 , H01L23/28 , H01L25/29 , H01L23/48 , H01L23/34 , H01L23/10
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L23/4334 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/05599 , H01L2224/0401
摘要： A method is provided of making a semiconductor package with a heat spreader in which a chip carrier module plate consisting of a plurality of array-arranged chip carriers is mounted with at least one chip on each of the chip carriers. A heat spreader module plate is attached to the chips, with an interface layer formed on a top surface of the heat spreader module plate. The chip carrier module plate, the chips and the heat spreader module plate are encapsulated. Adhesion force between the interface layer and the encapsulant is larger than that between the interface layer and the heat spreader module plate, and adhesion force between the interface layer and the heat spreader module plate is smaller than that between the heat spreader module plate and the encapsulant.
摘要翻译： 提供了一种制造具有散热器的半导体封装的方法，其中由多个阵列布置的芯片载体组成的芯片载体模块板在每个芯片载体上安装有至少一个芯片。 散热器模块板附接到芯片，其中界面层形成在散热器模块板的顶表面上。 芯片载体模块板，芯片和散热器模块板被封装。 界面层与密封剂之间的粘附力大于界面层与散热器模块板之间的粘合力，界面层与散热器模块板之间的粘合力小于散热器模块板与密封剂之间的粘附力 。
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公开(公告)号：US07132312B2
公开(公告)日：2006-11-07
申请号：US11338056
申请日：2006-01-23
申请人： Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/44
CPC分类号： H01L21/561 , H01L21/568 , H01L23/3121 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/20 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/18162 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： A semiconductor package having conductive bumps on a chip and a fabrication method thereof are provided. A plurality of the conductive bumps are deposited respectively on bond pads of the chip. An encapsulation body encapsulates the chip and conductive bumps while exposing ends of the conductive bumps. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the exposed ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings for exposing predetermined portions of the conductive traces. The exposed portions of the conductive traces are connected to a plurality of solder balls respectively. The conductive bumps on the bond pads of the chip allow easy positional recognition of the bond pads, making the conductive traces well electrically connected to the bond pads through the conductive bumps and assuring the quality and reliability of the semiconductor package.
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公开(公告)号：US20060223216A1
公开(公告)日：2006-10-05
申请号：US11208269
申请日：2005-08-18
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L27/14618 , H01L24/97 , H01L25/167 , H01L27/14625 , H01L27/14683 , H01L2224/32225 , H01L2224/48247 , H01L2224/73265 , H01L2924/181 , H01L2224/48091 , H01L2924/00014 , H01L2924/00
摘要： A sensor module structure and a method for fabricating the same are proposed. A chip carrier module plate including a plurality of chip carriers is provided, each chip carrier having a first surface and a second surface. At least one semiconductor chip is mounted on and electrically connected to the first surface of each of the chip carriers. An encapsulation body is formed for completely encapsulating the semiconductor chips and the first surfaces of the chip carriers. A singulation process is performed to form individual package units integrated with the semiconductor chips. A sensor chip, a corresponding lens kit and a flexible printed circuit (FPC) board are attached to the second surface of each of the chip carriers, wherein the sensor chip and the FPC board are electrically connected to the chip carrier. This provides the sensor module structure fabricated with simple processes, low costs and high yields.
摘要翻译： 提出了一种传感器模块结构及其制造方法。 提供了包括多个芯片载体的芯片载体模块板，每个芯片载体具有第一表面和第二表面。 至少一个半导体芯片安装在每个芯片载体的第一表面上并电连接到每个芯片载体的第一表面。 形成用于完全封装半导体芯片和芯片载体的第一表面的封装体。 执行单个处理以形成与半导体芯片集成的单个封装单元。 传感器芯片，相应的透镜套件和柔性印刷电路板（FPC）板安装在每个芯片载体的第二表面上，其中传感器芯片和FPC基板电连接到芯片载体。 这提供了以简单的工艺制造的传感器模块结构，低成本和高产量。
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公开(公告)号：USD529031S1
公开(公告)日：2006-09-26
申请号：US29210201
申请日：2004-07-27
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