公开(公告)号：US20250130490A1

公开(公告)日：2025-04-24

申请号：US18611138

申请日：2024-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Hui HSIEH ,  Boming HSU ,  Hsiang-Chien HSU ,  Chien-Hung LAI

IPC: G03F1/72 ,  C07F15/00 ,  C23C16/48 ,  G03F1/24 ,  G03F1/54

Abstract: A method for repairing a lithography mask is provided. The method includes receiving a lithography mask having a capping layer that includes a damaged region, identifying a location and a dimension of the damaged region of the capping layer, determining a repairing time duration based on the dimension of the damaged region of the capping layer, and forming a capping patch layer in the damaged region of the capping layer.

公开(公告)号：US20250130380A1

公开(公告)日：2025-04-24

申请号：US18431117

申请日：2024-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Chih-Wei Tseng ,  Jiun Yi Wu ,  Jui Lin Chao

IPC: G02B6/42

Abstract: Optical devices and methods of manufacture are presented in which glass interposers are incorporated with optical devices. In some embodiments a method includes forming a first optical package and then bonding the first optical package to a first glass interposer. The first glass interposer may then be connected to a second interposer.

公开(公告)号：US12283622B2

公开(公告)日：2025-04-22

申请号：US18342146

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Cheng-Po Chau ,  Yun Chen Teng

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/66

Abstract: A method for forming a semiconductor device and a semiconductor device formed by the method are disclosed. In an embodiment, the method includes depositing a dummy dielectric layer on a fin extending from a substrate; depositing a dummy gate seed layer on the dummy dielectric layer; reflowing the dummy gate seed layer; etching the dummy gate seed layer; and selectively depositing a dummy gate material over the dummy gate seed layer, the dummy gate material and the dummy gate seed layer constituting a dummy gate.

公开(公告)号：US12283613B2

公开(公告)日：2025-04-22

申请号：US18418678

申请日：2024-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US12283595B2

公开(公告)日：2025-04-22

申请号：US17655321

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Chen-Bin Lin ,  Wen-Hsin Chan

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238

Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.

公开(公告)号：US12283532B2

公开(公告)日：2025-04-22

申请号：US17866807

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Liang-Chor Chung

IPC: H01L21/66 ,  H01L21/768

Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

公开(公告)号：US12283485B2

公开(公告)日：2025-04-22

申请号：US17872623

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Wan-Hsien Lin ,  Chieh-Ping Wang ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/764 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.

公开(公告)号：US12282255B2

公开(公告)日：2025-04-22

申请号：US18739140

申请日：2024-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Kuosheng Chuang

IPC: H01L21/00 ,  G03F7/06 ,  H01L21/033

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

公开(公告)号：US12281385B2

公开(公告)日：2025-04-22

申请号：US14739355

申请日：2015-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Wei Zhang ,  Ching-Chia Wu ,  Wei-Jen Chen ,  Yen-Yu Chen

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/509

Abstract: A gas dispenser utilized in a deposition apparatus is provided. The gas dispenser includes a showerhead comprising a plurality of holes, and a mask layer formed on a surface of the showerhead, wherein the holes penetrate through the mask layer. A deposition apparatus using the gas dispenser is also disclosed.

公开(公告)号：US20250126883A1

公开(公告)日：2025-04-17

申请号：US18991919

申请日：2024-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H10D84/83 ,  H01L21/02 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H10D30/60 ,  H10D62/00 ,  H10D62/10 ,  H10D62/13 ,  H10D64/01 ,  H10D64/27 ,  H10D64/66 ,  H10D84/01 ,  H10D84/03

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.