公开(公告)号：US20020000036A1

公开(公告)日：2002-01-03

申请号：US09920967

申请日：2001-08-03

发明人： Osamu Takamatsu ,  Katsunori Hatanaka ,  Kiyoshi Takimoto ,  Haruki Kawada ,  Ken Eguchi ,  Yuko Morikawa ,  Hiroshi Matsuda ,  Toshihiko Takeda ,  Yoshihiro Yanagisawa ,  Hisaaki Kawade ,  Hideyuki Kawagishi

IPC分类号： H05K003/02 ,  H05K003/10 ,  G11B005/127

CPC分类号： B05D1/202 ,  B82Y30/00 ,  B82Y40/00 ,  G11B9/00 ,  G11B11/08 ,  Y10T29/49032 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

摘要： An electrode substrate and a recording medium having a smooth surface with surface unevenness of 1 nm or less and a size of 1 nullm/or more are disclosed. An electrode substrate and a recording medium having a concave-shaped groove for tracking on the surface, which groove has a depth which can detect of the tunnel current from the bottom thereof by a probe electrode for scanning the surface are also disclosed. Information processing devices equipped with the smooth recording medium, an electroconductive probe arranged approximate to the recording medium and a pulse voltage application circuit for recording are also disclosed.

摘要翻译： 具有1nm以下的表面凹凸平滑表面，1mum / <定制字符文件=“US20020000036A1-20020103-P00900.TIF”的电极基板和记录介质，wi =“20”= 20 “id =”custom-character-00001“/>或更多。 还公开了一种具有用于在表面上跟踪的凹形槽的电极基板和记录介质，该凹槽具有可以通过用于扫描该表面的探针电极从其底部检测隧道电流的深度。 还公开了配备有平滑记录介质的信息处理设备，近似于记录介质的导电探针和用于记录的脉冲电压施加电路。

公开(公告)号：US20010039728A1

公开(公告)日：2001-11-15

申请号：US09901838

申请日：2001-07-10

发明人： Salman Akram ,  Derek J. Gochnour ,  Michael E. Hess ,  David R. Hembree

IPC分类号： H05K003/02 ,  B26D003/00 ,  B23P017/00 ,  H05K003/10

CPC分类号： H01L21/67092 ,  B28D5/024 ,  B28D5/029 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49789 ,  Y10T29/49798 ,  Y10T83/0259 ,  Y10T83/04 ,  Y10T83/0524 ,  Y10T83/7809 ,  Y10T83/7868

摘要： A semiconductor wafer saw and method of using the same for dicing semiconductor wafers comprising a wafer saw including variable lateral indexing capabilities and multiple blades. The wafer saw, because of its variable indexing capabilities, can dice wafers having a plurality of differently sized semiconductor devices thereon into their respective discrete components. In addition, the wafer saw with its multiple blades, some of which may be independently laterally or vertically movable relative to other blades, can more efficiently dice silicon wafers into individual semiconductor devices.

公开(公告)号：US20010039720A1

公开(公告)日：2001-11-15

申请号：US09897998

申请日：2001-07-05

申请人： Kabushiki Kaisha Toshiba

发明人： Kenji Sasaoka ,  Fumitoshi Ikegaya ,  Takahiro Mori ,  Tomohisa Motomura ,  Yoshizumi Sato ,  Koichiro Shibayama

IPC分类号： B23P019/00 ,  H01R043/00 ,  B21B001/46 ,  H05K003/10

CPC分类号： B32B38/162 ,  B32B38/1858 ,  B32B2038/1891 ,  B32B2309/65 ,  B32B2457/08 ,  H05K3/1216 ,  H05K3/26 ,  H05K3/4069 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/066 ,  H05K2203/082 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/4922 ,  Y10T29/49991 ,  Y10T29/5136 ,  Y10T29/5137 ,  Y10T29/53061 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T29/53174 ,  Y10T29/53187 ,  Y10T29/532 ,  Y10T29/53243 ,  Y10T29/53261 ,  Y10T29/53539

摘要： The apparatus for manufacturing a wiring substitute comprises a transporter having a circuit where a sheet is circulated; a screen printer for printing a conductive paste on the sheet; a counter for counting the number of times to print the conductive paste on the sheet; and a distributor for ejecting the sheet from the circuit when the counted number reaches a preset number. Thus, the conductive pillars having uniform properties can be formed automatically on the conductive foil with high productivity.

摘要翻译： 用于制造布线替代品的装置包括具有片材循环的电路的运送器; 用于在片材上印刷导电膏的丝网印刷机; 用于计数在片材上印刷导电糊的次数的计数器; 以及当计数的数量达到预设数量时从电路中弹出纸张的分配器。 因此，可以以高生产率自动地在导电箔上形成具有均匀性质的导电柱。

公开(公告)号：US20040163246A1

公开(公告)日：2004-08-26

申请号：US10717718

申请日：2003-11-21

申请人： Renesas Technology Corp. ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Yasutaka Nishioka ,  Junjiro Sakai ,  Shingo Tomohisa ,  Susumu Matsumoto ,  Fumio Iwamoto ,  Michinari Yamanaka

IPC分类号： H05K003/10

CPC分类号： H01L21/76808 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

摘要： It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400null C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate. Consequently, a by-product staying in an interface of an upper protective film (6) and an interlayer dielectric film (5) having a low dielectric constant and a by-product staying in an interface of the etching stopper film (4) and the interlayer dielectric film (5) having a low dielectric constant are discharged so that an amount of the residual by-product can be decreased.

摘要翻译： 本发明的目的是提供一种具有掩埋多层布线结构的半导体器件，其中抗蚀剂图案的分辨率缺陷的产生被抑制，并且由分辨率缺陷引起的缺陷布线的产生减少。 在形成到达蚀刻停止膜（4）的通孔（7）之后，在通孔（7）打开的情况下，在300〜400℃进行退火。 作为退火方法，可以使用使用热板的方法和使用热处理炉的方法。 为了抑制对制造的下布线（20）的影响，通过使用热板进行约5〜10分钟的短时间的加热。 因此，残留在上部保护膜（6）和具有低介电常数的副产物残留在蚀刻阻挡膜（4）的界面上的层间电介质膜（5）的界面中的副产物和 排出具有低介电常数的层间绝缘膜（5），从而可以减少残留副产物的量。

公开(公告)号：US20040148770A1

公开(公告)日：2004-08-05

申请号：US10762004

申请日：2004-01-21

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Masahide Tsukamoto ,  Masanaru Hasegawa ,  Hideo Hatanaka

IPC分类号： H05K003/10 ,  H05K001/11

CPC分类号： H05K3/462 ,  H05K3/205 ,  H05K3/207 ,  H05K3/4069 ,  H05K3/4652 ,  H05K3/4658 ,  H05K2201/0116 ,  H05K2201/0376 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/1461 ,  Y10S156/923 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T156/1168

摘要： A method for producing printed wiring boards comprises the steps of perforating through holes at predetermined positions in an adhesive insulator sheet, filling the through holes with a conductive material such as a conductive paste or metal balls, transferring conductive wiring patterns that have been formed on surfaces of releasable supporting sheets onto the surfaces of the adhesive insulator sheet by heat and pressure. Simultaneously, interlayer via-connections are performed by means of the conductive material filled into the through holes.

摘要翻译： 一种制造印刷电路板的方法包括以下步骤：在粘合绝缘片中的预定位置穿孔，在导电材料如导电膏或金属球填充通孔，转印形成在表面上的导电布线图案 通过热和压力将可释放的支撑片材粘合到绝缘片的表面上。 同时，通过填充到通孔中的导电材料进行层间通孔连接。

公开(公告)号：US20030192183A1

公开(公告)日：2003-10-16

申请号：US10418510

申请日：2003-04-16

发明人： Reed Gleason ,  Michael A. Bayne ,  Kenneth Smith

IPC分类号： H05K003/36 ,  H05K003/02 ,  H05K003/10

CPC分类号： G01R1/06744 ,  G01R1/06738 ,  G01R1/0735 ,  G01R3/00 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09736 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49815

摘要： A substrate, preferably constructed of a ductile material and a tool having the desired shape of the resulting device for contacting contact pads on a test device is brought into contact with the substrate. The tool is preferably constructed of a material that is harder than the substrate so that a depression can be readily made therein. A dielectric (insulative) layer, that is preferably patterned, is supported by the substrate. A conductive material is located within the depressions and then preferably lapped to remove excess from the top surface of the dielectric layer and to provide a flat overall surface. A trace is patterned on the dielectric layer and the conductive material. A polyimide layer is then preferably patterned over the entire surface. The substrate is then removed by any suitable process.

摘要翻译： 优选由延性材料构成的基板和具有用于接触测试装置上的接触焊盘的所得装置的所需形状的工具与基板接触。 该工具优选地由比基板更硬的材料构成，使得可以容易地在其中形成凹陷。 优选图案化的电介质（绝缘）层由衬底支撑。 导电材料位于凹陷内，然后优选地研磨以从电介质层的顶表面去除多余的并提供平坦的总体表面。 在电介质层和导电材料上形成迹线。 然后优选在整个表面上图案化聚酰亚胺层。 然后通过任何合适的方法去除衬底。

公开(公告)号：US20030150111A1

公开(公告)日：2003-08-14

申请号：US10366425

申请日：2003-02-13

发明人： Belgacem Haba ,  Konstantine Karavakis

IPC分类号： H05K003/10 ,  H01R043/16

CPC分类号： H05K3/4092 ,  H01L23/32 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/3011 ,  Y10T29/49121 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49222 ,  Y10T29/49224 ,  H01L2924/00

摘要： A connection component for making connections to a microelectronic element is made by providing leads on a surface of a polymeric layer and etching the polymeric layer to partially detach the leads from the polymeric layer, leaving a portion of each lead releasably connected to the polymeric layer by a small polymeric connecting element which can be broken or peeled away from the lead. Leads in a connecting element may be covered by an insulating jacket applied by a coating process, and the insulating jacket may in turn be covered by a conductive layer so that each lead becomes a miniature coaxial cable. This arrangement provides immunity to interference and facilitates operation at high speeds.

公开(公告)号：US20030061711A1

公开(公告)日：2003-04-03

申请号：US09964810

申请日：2001-09-28

发明人： Christopher N. Olsen

IPC分类号： H01K003/10 ,  H05K003/10 ,  G05F001/00

CPC分类号： H05K1/0216 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/09236 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

摘要： A method is provided for designing a printed circuit board. This may include analyzing at least one characteristic of a first plurality of relatively parallel conductive paths on the printed circuit board. The first plurality of relatively parallel conductive paths may be arranged in a pattern in a first area of the printed circuit board. The method may also include rearranging the pattern of conductive paths such that a second plurality of relatively parallel conductive paths in a second area of the printed circuit board have a different geometry or arrangement with respect to one another as compared to a geometry or arrangement of the first plurality of relatively parallel conductive paths in the first area.

摘要翻译： 提供了一种用于设计印刷电路板的方法。 这可以包括分析印刷电路板上的第一多个相对平行的导电路径的至少一个特征。 第一多个相对平行的导电路径可以布置在印刷电路板的第一区域中的图案中。 该方法还可以包括重新布置导电路径的图案，使得印刷电路板的第二区域中的第二多个相对平行的导电路径相对于彼此具有不同的几何形状或布置，与 在第一区域中的第一多个相对平行的导电路径。

公开(公告)号：US20030047350A1

公开(公告)日：2003-03-13

申请号：US09954402

申请日：2001-09-11

发明人： Brian S. Forbes

IPC分类号： H05K003/10

CPC分类号： H05K1/0266 ,  H05K1/185 ,  H05K2201/10159 ,  Y10T29/49155

摘要： A method of tracking a printed circuit board is described. An embedded identification device is utilized. The embedded identification device is placed in a layer of the printed circuit board. An external transceiver is used to communicate with the embedded device and record platform information.

摘要翻译： 描述了跟踪印刷电路板的方法。 使用嵌入式识别装置。 将嵌入式识别装置放置在印刷电路板的一层中。 外部收发器用于与嵌入式设备通信并记录平台信息。

公开(公告)号：US20030037434A1

公开(公告)日：2003-02-27

申请号：US10242022

申请日：2002-09-12

申请人： DOWA MINING CO., LTD.

发明人： Hideyo Osanai ,  Masahiro Furo

IPC分类号： H05K003/20 ,  H05K003/34 ,  H05K003/10

CPC分类号： H05K3/0061 ,  B32B2311/12 ,  B32B2311/24 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/16 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/407 ,  H01L23/142 ,  H01L23/3735 ,  H01L24/83 ,  H01L2224/32225 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/101 ,  H05K3/38 ,  H05K2203/128 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49222 ,  H01L2924/00

摘要： A metal-ceramic circuit board is characterized by being constituted by bonding on a base plate of aluminum or aluminum alloy at least one of ceramic substrate boards having a conductive metal member for an electronic circuit. A method of manufacturing a metal-ceramic circuit board is characterized by comprising the steps of melting aluminum or aluminum alloy in a vacuum or inert gas atmosphere to form a molten metal, contacting one surface of a ceramic substrate board directly with the molten metal in a vacuum or inert gas atmosphere, cooling the molten metal and the ceramic substrate board to form a base plate of aluminum or aluminum alloy, which is bonded directly on the ceramic substrate board without forming any oxidizing film therebetween and bonding a conductive metal member for an electronic circuit on the ceramic substrate board by using a brazing material. The base plate has a proof stress not higher than 320 (MPa) and a thickness not smaller than 1 mm.