公开(公告)号：US12125533B2

公开(公告)日：2024-10-22

申请号：US17812122

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

公开(公告)号：US20240348242A1

公开(公告)日：2024-10-17

申请号：US18627197

申请日：2024-04-04

Applicant: STMicroelectronics International N.V.

Inventor： Enrico POLI ,  Vincenzo MARANO ,  Andrija FEHER ,  Pekka Sakari ALASAARI

IPC: H03K17/082 ,  H03K17/22 ,  H03K19/21

CPC classification number: H03K17/082 ,  H03K17/22 ,  H03K19/21 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A safety circuit for a gate driver device receives PWM driving signals, a system supply voltage, as well as first and second safety signals. The circuit includes a first logic circuit configured to propagate the PWM driving signals to produce gate driving signals if the first safety signal is de-asserted, and disable propagation of the PWM driving signals and de-assert the gate driving signals if the first safety signal is asserted. The circuit includes a second logic circuit configured to couple a power supply output node to the system supply voltage to produce a driver supply voltage if the second safety signal is de-asserted, and decouple the power supply output node from the system supply voltage if the second safety signal is asserted.

公开(公告)号：US20240332376A1

公开(公告)日：2024-10-03

申请号：US18614365

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Davide FAGIANI ,  Simone Dario MARIANI ,  Magali GREGOIRE ,  Théo Cabaret

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/41708 ,  H01L29/456 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: Integrated electronic device including: a semiconductor body of silicon delimited by a front surface and including at least a first semiconductive region of a first conductivity type, which extends into the semiconductor body starting from the front surface, and a second semiconductive region of a second conductivity type, which extends below the first semiconductive region; a dielectric capping region; a trench which extends through the dielectric capping region and through a front portion of the semiconductor body, in such a way that a part of the first semiconductive region laterally faces the trench, said trench partly extending inside the second semiconductive region; a conductive contact structure extending into the trench and including: a coating region of titanium silicide, which coats the bottom of the trench, in contact with the second semiconductive region, and also laterally coats the part of the first semiconductive region laterally facing the trench; and an inner conductive region.

公开(公告)号：US20240332210A1

公开(公告)日：2024-10-03

申请号：US18618447

申请日：2024-03-27

Applicant: STMicroelectronics International N.V.

Inventor： Patrick LAURENT ,  Jean-Michel RIVIERE

IPC: H01L23/552 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/16

CPC classification number: H01L23/552 ,  H01L31/02016 ,  H01L31/0203 ,  H01L31/16

Abstract: An integrated circuit optical package includes a support substrate having a mounting face and an electrical interconnection network between the mounting face and contact pads located on a lower face of the support substrate. A cap includes a lateral wall fastened on the mounting face and an upper wall including a first opening. A first optical element is fastened on the upper wall of the cap to seal the first opening. An electromagnetic shielding element is embedded in the cap and configured to be coupled to a reference supply point via the interconnection network and at least one contact pad. A first electronic chip is mounted on the mounting face and in optical cooperation with the first optical element.

公开(公告)号：US20240332011A1

公开(公告)日：2024-10-03

申请号：US18614538

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Björn MAGNUSSON LINDGREN ,  Alexandre ELLISON ,  Carlo RIVA

IPC: H01L21/02 ,  C30B28/14 ,  C30B29/36

CPC classification number: H01L21/02378 ,  C30B28/14 ,  C30B29/36 ,  H01L21/02433 ,  H01L21/0262

Abstract: At least one embodiment of a method of manufacturing includes forming a first polycrystalline silicon carbide (SiC) substrate with a sintering process by sintering one or more powdered semiconductor materials. After the first polycrystalline SiC substrate is formed utilizing the sintering process, the first polycrystalline silicon carbide SiC substrate is utilized to form a second polycrystalline SiC substrate with a chemical vapor deposition (CVD) process. The second polycrystalline SiC substrate is formed on a surface of the first polycrystalline SiC substrate by depositing SiC on the surface of the first polycrystalline SiC substrate with the CVD process. As the first and second polycrystalline SiC substrates are made of the same or similar semiconductor material (e.g., SiC), a first coefficient of thermal expansion (CTE) for the first polycrystalline SiC substrate is the same or similar to the second CTE of the second polycrystalline SiC substrate.

公开(公告)号：US20240330677A1

公开(公告)日：2024-10-03

申请号：US18192589

申请日：2023-03-29

Applicant: STMicroelectronics International N.V.

Inventor： Carmine CAPPETTA ,  Paolo Sergio ZAMBOTTI ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.

公开(公告)号：US20240330399A1

公开(公告)日：2024-10-03

申请号：US18194108

申请日：2023-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Carmine CAPPETTA ,  Surinder Pal SINGH ,  Giuseppe DESOLI ,  Thomas BOESCH

IPC: G06F17/15

CPC classification number: G06F17/15

Abstract: A neural network includes an internal storage unit. The internal storage unit stores feature data received from a memory external to the neural network. The internal storage unit reads the feature data to a hardware accelerator of the neural network. The internal storage unit adapts a storage pattern of the feature data and a read pattern of the feature data to enhance the efficiency of the hardware accelerator.

公开(公告)号：US20240329125A1

公开(公告)日：2024-10-03

申请号：US18616929

申请日：2024-03-26

Applicant: STMicroelectronics International N.V.

Inventor： Moise AVOCI UGWIRI ,  Giuliano FILPI ,  Fabrice COSTE ,  Alex GRIMA ,  Pedro Jr Santos PERALTA

IPC: G01R31/28 ,  H01L23/00

CPC classification number: G01R31/2887 ,  H01L24/75 ,  H01L24/81 ,  G01R31/2896 ,  H01L2224/75745 ,  H01L2224/75756 ,  H01L2224/81136 ,  H01L2224/8118

Abstract: A method and apparatus for aligning electrical contact formations, such as bumps or solder balls, at a first surface of a Wafer Level Chip Scale Package (WLCSP) semiconductor device with electrically conductive pins in an array of electrically conductive pins such as “pogo” pins is provided. The semiconductor device includes, opposite the first surface, a second surface protected by a protection layer. The method includes aligning the semiconductor device to a first alignment member by exposing the protected second surface of the semiconductor device to a chamfered surface in the first alignment member. A second alignment member is aligned to the array of electrically conductive pins. The electrical contact formations are aligned with respect to the array of electrically conductive pins as desired in response to the first and second alignment members being mutually aligned, in response to the semiconductor device being “landed” onto the array of electrically conductive pins.

公开(公告)号：US20240327199A1

公开(公告)日：2024-10-03

申请号：US18614435

申请日：2024-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Paola CARULLI ,  Patrick FEDELI ,  Luca Giuseppe FALORNI ,  Federico MORELLI

IPC: H02K33/00 ,  B81B3/00

CPC classification number: B81B3/0051 ,  B81B2201/0235 ,  B81B2201/0242

Abstract: Microelectromechanical device comprising a supporting body, containing semiconductor material and a movable mass, constrained to the supporting body with a relative degree of freedom with respect to at least one motion direction, within a range of admissible positions. The device also comprises stopper elements, operable by the movable mass due to movements along the at least one motion direction and configured to apply stop forces to opposite sides of the movable mass, transversely to the at least one motion direction, when the movable mass reaches a respective endpoint of the range of admissible positions, so as to prevent the movable mass from exceeding the respective endpoint.

公开(公告)号：US20240322814A1

公开(公告)日：2024-09-26

申请号：US18604239

申请日：2024-03-13

Applicant: STMicroelectronics International N.V.

Inventor： Francesco PULVIRENTI ,  Salvatore Giuseppe PRIVITERA ,  Cesare BIMBI

IPC: H03K17/16 ,  H03K17/10 ,  H03K17/687

CPC classification number: H03K17/162 ,  H03K17/102 ,  H03K17/6872

Abstract: A buffer circuit for driving a GaN power switch includes an input node to receive an input signal and an output node to produce a gate signal for the GaN power switch. The buffer includes a push-pull stage that includes a first transistor coupled between a supply voltage node and the output node, a second transistor coupled between the supply voltage node and the output node, a third transistor coupled between the output node and a reference voltage node, and a fourth transistor coupled between the output node and the reference voltage node. The buffer includes a pre-buffer stage configured to receive the input signal and to produce respective driving signals for the first, second, third and fourth transistors to produce the gate signal at the output node in four consecutive phases.