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    EEPROM architecture wherein each bit is formed by two serially connected cells
    561.
    发明授权
    EEPROM architecture wherein each bit is formed by two serially connected cells 有权
    EEPROM架构，其中每个位由两个串行连接的单元形成

    公开(公告)号：US09514820B2

    公开(公告)日：2016-12-06

    申请号：US14547199

    申请日：2014-11-19

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G11C16/00 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  G11C29/08 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50

    CPC classification number: G11C16/0483 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C29/08 ,  G11C29/50004 ,  H01L27/11519 ,  H01L27/11524

    Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

    Abstract translation: 集成电路存储器包括以行和列排列成阵列的存储单元，每列包括第一位线和第二位线。 每个存储单元由以下部分形成：具有第一源极 - 漏极路径的第一选择晶体管; 具有第二源极 - 漏极路径的第二选择晶体管; 具有第三源极 - 漏极路径的第一浮栅晶体管; 以及具有第四源极 - 漏极路径的第二浮栅晶体管。 第一，第二，第三和第四源极 - 漏极路径串联耦合在第一位线和第二位线之间。 存储器的每行的字线被耦合到第一和第二选择晶体管的栅极端子。 耦合到第一和第二浮栅晶体管的栅极端的每行的控制栅极线。

    METHOD OF COMMUNICATION OVER A TWO-WIRE BUS
    562.
    发明申请
    METHOD OF COMMUNICATION OVER A TWO-WIRE BUS 审中-公开
    双线总线通讯方式

    公开(公告)号：US20160344563A1

    公开(公告)日：2016-11-24

    申请号：US14984073

    申请日：2015-12-30

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Yvon Bahout

    IPC: H04L12/10

    CPC classification number: H04L12/10 ,  G06F13/4291

    Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

    Abstract translation: 一种通过具有时钟线和数据线的双线总线耦合在一起的第一电路和第二电路之间的通信方法。 通过将时钟线和数据线设置为不同的电位电平，通过双线总线将电源信号提供给第二电路。 将第一电路和第二电路中的一个发送到第一电路和第二电路中的另一个，通过根据当设置时钟线时要发送的位的状态将数据线设置为电位电平 处于第一潜在水平。 响应于时钟线从第一电位电平到不同于第一电位电平的第二电位电平而读取一位。

    Modular cell for a memory array, the modular cell including a memory circuit and a read circuit
    563.
    发明授权
    Modular cell for a memory array, the modular cell including a memory circuit and a read circuit 有权
    用于存储器阵列的模块化单元，所述模块单元包括存储器电路和读取电路

    公开(公告)号：US09502110B1

    公开(公告)日：2016-11-22

    申请号：US14964156

    申请日：2015-12-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francois Tailliet

    IPC: G11C11/34 ,  G11C14/00 ,  G11C16/26 ,  G11C11/419

    CPC classification number: G11C14/0063 ,  G11C11/412 ,  G11C11/419 ,  G11C16/26

    Abstract: A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.

    Abstract translation: 在存储器阵列中使用的存储单元包括存储器电路和读取电路。 存储电路包括耦合到RS触发器的非易失性存储器元件（例如，浮栅晶体管）。 RS触发器配置有耦合以接收第一使能信号的p沟道晶体管和耦合以接收第二使能信号的n沟道晶体管。 使能信号的断言在时间上偏移以控制用于将锁存器节点强制到特定电压并使能锁存操作的操作。 读取电路包括耦合到RS触发器的输出并可用作读出放大器电路的锁存电路。 存储器和读取电路在矩形电路区域内制造。 许多这样的矩形电路区域可以位于存储器阵列的行或列中彼此相邻的位置。

    PROTECTION OF REGISTERS AGAINST UNILATERAL DISTURBANCES
    564.
    发明申请
    PROTECTION OF REGISTERS AGAINST UNILATERAL DISTURBANCES 审中-公开
    保护防止非法作战的登记

    公开(公告)号：US20160308673A1

    公开(公告)日：2016-10-20

    申请号：US14671019

    申请日：2015-03-27

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pierre-Yvan Liardet ,  Yannick Teglia ,  Jerome Tournemille

    IPC: H04L9/08

    CPC classification number: G06F21/75 ,  G06F21/72 ,  G06F2221/2105 ,  H04L9/004

    Abstract: A device includes one or more registers and circuitry. The circuitry subjects a key having a number of bits to a first function which takes a selection value into account, generating a result having a number of bits which is twice the number of bits of the key, and stores the result in the one or more registers. In response to a call for the key, the circuitry subjects the result stored in the one or more registers to a second function which takes the selection value into account to generate a response having a same value as the key.

    Abstract translation: 设备包括一个或多个寄存器和电路。 该电路将具有多个比特的密钥作为考虑到选择值的第一功能，产生具有该密钥比特数的两倍的比特数的结果，并将该结果存储在一个或多个 注册 响应于对键的调用，电路对存储在一个或多个寄存器中的结果进行考虑到选择值的第二函数，以产生具有与该键相同的值的响应。

    Page or word-erasable composite non-volatile memory
    565.
    发明授权
    Page or word-erasable composite non-volatile memory 有权
    页面或字可擦除复合非易失性存储器

    公开(公告)号：US09460798B2

    公开(公告)日：2016-10-04

    申请号：US14795742

    申请日：2015-07-09

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Francesco La Rosa

    IPC: G11C16/04 ,  G11C16/14 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115 ,  G11C16/08 ,  G11C16/26

    CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased.

    Abstract translation: 非易失性存储器包括位线，包括第一类型的存储器单元的第一可寻址扇区和包括第二类型的存储单元的第二可擦除或可位可擦除扇区。 第一类型的存储单元包括单个浮栅晶体管，并且第二类型的存储单元包括第一浮栅晶体管和浮置栅电耦合的第二浮栅晶体管，第二浮栅 第二种类型的存储器单元的晶体管使得能够单独地擦除存储单元。

    METHOD FOR AUTHENTICATION OF AN OBJECT BY A DEVICE CAPABLE OF MUTUAL CONTACTLESS COMMUNICATION, CORRESPONDING SYSTEM AND OBJECT
    566.
    发明申请
    METHOD FOR AUTHENTICATION OF AN OBJECT BY A DEVICE CAPABLE OF MUTUAL CONTACTLESS COMMUNICATION, CORRESPONDING SYSTEM AND OBJECT 审中-公开
    通过相互联系通信的设备验证对象的方法，相应的系统和对象

    公开(公告)号：US20160226665A1

    公开(公告)日：2016-08-04

    申请号：US14929566

    申请日：2015-11-02

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Sylvie WUIDART

    IPC: H04L9/30 ,  H04L9/08 ,  H04W12/02 ,  H04L9/00

    CPC classification number: H04L9/3066 ,  G06F21/44 ,  G06F21/73 ,  G06F2221/2129 ,  H04L9/3247 ,  H04L63/0823 ,  H04L2209/046 ,  H04L2209/805 ,  H04W12/02

    Abstract: An object stores a signature associated therewith. An authentication method includes generating in the object at least one piece of personalized information of the object based on the stored signature and on at least one indication associated with the object, and communicating without contact by a device to the object during the authentication. The method also includes contactless communications to the device of the at least one piece of personalized information, determining by the device the signature based on at least the one piece of personalized information and on the at least one indication, and verifying the signature by the device.

    Abstract translation: 对象存储与其相关联的签名。 认证方法包括：根据所存储的签名和关于对象的至少一个指示，在对象中生成对象的至少一条个性化信息，以及在认证期间通过设备与对象进行通信。 该方法还包括至少一条个性化信息到设备的非接触式通信，由设备基于至少一条个性化信息和该至少一个指示来确定签名，并且验证该设备的签名 。

    Electrically controllable integrated switch
    569.
    发明授权
    Electrically controllable integrated switch 有权
    电控集成开关

    公开(公告)号：US09355802B2

    公开(公告)日：2016-05-31

    申请号：US14286331

    申请日：2014-05-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

    IPC: H01H59/00 ,  H01L27/06 ,  H01L21/822 ,  H01H1/00 ,  H01L23/522

    CPC classification number: H01H59/0009 ,  B81B2201/018 ,  B81C1/00246 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01H1/0036 ,  H01H57/00 ,  H01H2001/0068 ,  H01H2001/0078 ,  H01H2059/0054 ,  H01L21/8221 ,  H01L23/522 ,  H01L27/0617 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit includes an interconnection part with several metallization levels. An electrically activatable switching device within the interconnection part has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

    Abstract translation: 集成电路包括具有多个金属化级别的互连部件。 互连部件内的可电激活的开关装置具有包括由结构保持的梁的组件。 梁和结构位于相同的金属化水平内。 布置结构在梁上的固定位置，以便为梁定义位于这些固定位置之间的枢转点。 该结构在不存在电位差的情况下相对于光束和垂直于光束的平面基本对称。 在存在施加在结构的第一部分之间的第一电位差并且在存在施加在结构的第二部分之间的第二电位差的情况下在第二方向上枢转时，梁能够在第一方向上枢转。

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