公开(公告)号：US12243429B2

公开(公告)日：2025-03-04

申请号：US17306449

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： Arvind Merwaday ,  Leonardo Gomes Baltar ,  Kathiravetpillai Sivanesan ,  May Wu ,  Suman A. Sehra

IPC: G08G1/00 ,  B60W30/09 ,  B60W30/16

Abstract: Techniques are disclosed to increase the safety of vehicles travelling in a vehicle platoon. These techniques include the utilization of a comprehensive safety framework such as a safety driving model (SDM) for the platoon control systems. In contrast to the conventional approaches, the use of the SDM model allows for platoon vehicle control systems to consider the acceleration/deceleration capabilities of the vehicles to calculate minimum safe longitudinal distances between the platoon vehicles. The disclosed techniques may utilize the periodicity of platoon messages as well as other parameters to improve upon platoon vehicle control and safety.

公开(公告)号：US12243155B2

公开(公告)日：2025-03-04

申请号：US17357423

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Ronald Silvas ,  Karol A. Szerszen

IPC: G06T15/50 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/04 ,  G06T15/80

Abstract: Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.

公开(公告)号：US12243037B2

公开(公告)日：2025-03-04

申请号：US17697748

申请日：2022-03-17

Applicant: Intel Corporation

Inventor： Farid Adrangi ,  Sanjay Bakshi ,  Amit S. Bodas

IPC: G06Q20/20 ,  G07G1/00 ,  G07G1/14

Abstract: Logic to register a personal point of sale (POS) device. Logic may communicate with the registration processor to establish a secure communication channel. Logic may access a basic input output system to obtain platform information. Logic may transmit the platform information to the registration processor to identify a certification associated with the device. Logic may communicate with a payment instrument via a card reader. Logic may transmit an encrypted message from the card reader to the registration processor to bind the payment instrument to the device. Logic may receive a communication from the device comprising platform information. Logic may perform a security protocol to establish a secure communication channel with the device. Logic may determine an existence of the certification for the device in the database based upon the platform information. And logic may register the platform in response to locating the certification of the platform.

公开(公告)号：US12242290B2

公开(公告)日：2025-03-04

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20250072078A1

公开(公告)日：2025-02-27

申请号：US18940382

申请日：2024-11-07

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Joseph STEIGERWALD ,  Jinhong SHIN ,  Vinay CHIKARMANE ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H10B10/00

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20250071924A1

公开(公告)日：2025-02-27

申请号：US18940819

申请日：2024-11-07

Applicant: Intel Corporation

Inventor： Phil Geng ,  David Shia ,  Xiang Li ,  George Vergis ,  Ralph Miele ,  Sanjoy Saha ,  Jeffory Smalley

IPC: H05K7/14

Abstract: Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.

公开(公告)号：US20250071037A1

公开(公告)日：2025-02-27

申请号：US18947112

申请日：2024-11-14

Applicant: Intel Corporation

Inventor： Daniel Biederman ,  Patrick Connor ,  Karthik Kumar ,  Marcos Carranza ,  Anjali Singhai Jain

IPC: H04L43/0823 ,  G11C7/10

Abstract: Management of data transfer for network operation is described. An example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or missing data on the network, and circuitry to implement one or more data modifications for delayed or missing data on the network, including circuitry to provide replacement data for the delayed or missing data on the network.

公开(公告)号：US20250070083A1

公开(公告)日：2025-02-27

申请号：US18942054

申请日：2024-11-08

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20250070030A1

公开(公告)日：2025-02-27

申请号：US18943420

申请日：2024-11-11

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Ram VISWANATH ,  Xavier Francois BRUN ,  Tarek A. IBRAHIM ,  Jason M. GAMBA ,  Manish DUBEY ,  Robert Alan MAY

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20250069539A1

公开(公告)日：2025-02-27

申请号：US18738798

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Perazhi Sameer Kalathil ,  Vishal Ravindra Sinha ,  Krishna Kishore Nidamanuri ,  Mallari C. Hanchate ,  Vivek Paranjape ,  Kunjal S. Parikh ,  Roland P. Wooster

IPC: G09G3/20

Abstract: In one embodiment, a display panel may have multiple regions that are controlled by independent driver circuitries to allow for independent refreshing of different regions. Circuitry, e.g., in a graphics source or in the display, can determine, based on a partial frame update, which panel regions to refresh and refresh those regions, e.g., while not refreshing other regions of the panel.