公开(公告)号：US20240127903A1

公开(公告)日：2024-04-18

申请号：US18474643

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Torsten Partsch

IPC: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

公开(公告)号：US11960438B2

公开(公告)日：2024-04-16

申请号：US17410786

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Michael Raymond Miller

IPC: G06F15/80

CPC classification number: G06F15/8061

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

公开(公告)号：US20240119001A1

公开(公告)日：2024-04-11

申请号：US18377597

申请日：2023-10-06

Applicant: Rambus Inc.

Inventor： Taeksang Song ,  Christopher Haywood ,  Evan Lawrence Erickson

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: Disclosed are techniques for storing data decompressed from the compressed pages of a memory block when servicing data access request from a host device of a memory system to the compressed page data in which the memory block has been compressed into multiple compressed pages. A cache buffer may store the decompressed data for a few compressed pages to save decompression memory space. The memory system may keep track of the number of accesses to the decompressed data in the cache and the number of compressed pages that have been decompressed into the cache to calculate a metric associated with the frequency of access to the compressed pages within the memory block. If the metric does not exceed a threshold, additional compressed pages are decompressed into the cache. Otherwise, all the compressed pages within the memory block are decompressed into a separately allocated memory space to reduce data access latency.

公开(公告)号：US11955198B2

公开(公告)日：2024-04-09

申请号：US18097459

申请日：2023-01-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1045 ,  G11C7/1087 ,  G11C2207/105

Abstract: A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

公开(公告)号：US11955161B2

公开(公告)日：2024-04-09

申请号：US18103386

申请日：2023-01-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/00 ,  Y02D30/50

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20240111625A1

公开(公告)日：2024-04-04

申请号：US18233250

申请日：2023-08-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/10 ,  G06F11/16 ,  G11C7/10 ,  G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  H03M13/15

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  H03M13/1575 ,  G06F11/20

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

公开(公告)号：US11947471B2

公开(公告)日：2024-04-02

申请号：US17852135

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Brent Haukness

IPC: G06F13/16 ,  G06F5/14

CPC classification number: G06F13/1626 ,  G06F5/14

Abstract: A memory module includes at least two memory devices. Each of the memory devices perform verify operations after attempted writes to their respective memory cores. When a write is unsuccessful, each memory device stores information about the unsuccessful write in an internal write retry buffer. The write operations may have only been unsuccessful for one memory device and not any other memory devices on the memory module. When the memory module is instructed, both memory devices on the memory module can retry the unsuccessful memory write operations concurrently. Both devices can retry these write operations concurrently even though the unsuccessful memory write operations were to different addresses.

公开(公告)号：US20240103758A1

公开(公告)日：2024-03-28

申请号：US18367241

申请日：2023-09-12

Applicant: Rambus Inc.

Inventor： J. James TRINGALI

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0608 ,  G06F3/0679

Abstract: A buffer/interface device of the memory node may read and compress blocks of data (e.g., pages). When a memory buffer device compresses a block of data, it may keep storing the original uncompressed version in the original memory location (e.g., physical memory page). In this manner, an access directed to the block of data may be satisfied with the uncompressed version retrieved from the original memory location (e.g., physical memory page) without having to perform a decompression operation. As memory space is needed for other purposes (e.g., for an uncompressed copy of a recently decompressed block or as host allocated memory occupies more space), the original uncompressed versions of blocks (pages) that have not been accessed relatively recently (e.g., relative to other kept original uncompressed versions) may be evicted and replaced by other blocks of data (e.g., either compressed or uncompressed).

公开(公告)号：US20240097880A1

公开(公告)日：2024-03-21

申请号：US18039865

申请日：2021-11-30

Applicant: RAMBUS INC.

Inventor： Pascal VAN LEEUWEN

IPC: H04L9/06

CPC classification number: H04L9/0631

Abstract: Disclosed embodiments relate to cipher accelerator circuit comprising: a first affine transformation circuit generating a first data block from an input data block, a SM4 S-box circuit configured to perform a first byte S-box operation according to a SM4 cipher and using a SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substituted data block; and a second affine transformation circuit generating a second data block from the substituted data block, wherein the first and second affine transformation circuits are configured to perform multiplication of the substituted data block by a respective matrix and addition of a respective translation vector, and wherein the first and second affine transformations circuits are configured such that the second transformed data block is equal to the input data block processed by a second S-box operation according to another symmetric cipher using S-box tables.

公开(公告)号：US20240078044A1

公开(公告)日：2024-03-07

申请号：US18371300

申请日：2023-09-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F13/4282

Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.