Clock phase shift circuit
    51.
    发明授权
    Clock phase shift circuit 有权
    时钟相移电路

    公开(公告)号:US09531355B1

    公开(公告)日:2016-12-27

    申请号:US14754778

    申请日:2015-06-30

    Inventor: Yong Feng Liu

    CPC classification number: H03K5/00 H03K5/135 H03K2005/00202

    Abstract: An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

    Abstract translation: 电子设备包括第一电路,用于响应于具有第一逻辑电平的输入信号,当接收输入电流的第一电容器两端的第一电压超过阈值电压时产生输出控制信号。 输入电流与输入信号的频率成比例。 第二电路是响应于输入信号具有第二逻辑电平而在接收输入电流的第二电容器两端的第二电压超过阈值电压时产生输出复位信号。 触发器是响应于输出控制信号而产生具有第一逻辑电平的信号输出,并且响应于输出复位信号复位并产生具有第二逻辑电平的信号输出。

    CLOCK PHASE SHIFT CIRCUIT
    52.
    发明申请
    CLOCK PHASE SHIFT CIRCUIT 有权
    时钟相移电路

    公开(公告)号:US20160373093A1

    公开(公告)日:2016-12-22

    申请号:US14754778

    申请日:2015-06-30

    Inventor: Yong Feng Liu

    CPC classification number: H03K5/00 H03K5/135 H03K2005/00202

    Abstract: An electronic device includes a first circuit to generate an output control signal when a first voltage across a first capacitor receiving an input current exceeds a threshold voltage, in response to an input signal having a first logic level. The input current is proportional to a frequency of the input signal. A second circuit is to generate an output reset signal when a second voltage across a second capacitor receiving the input current exceeds the threshold voltage, in response to the input signal having a second logic level. A flip flop is to generate a signal output as having the first logic level in response to the output control signal, and to reset and generate the signal output as having the second logic level in response to the output reset signal.

    Abstract translation: 电子设备包括第一电路,用于响应于具有第一逻辑电平的输入信号,当接收输入电流的第一电容器两端的第一电压超过阈值电压时产生输出控制信号。 输入电流与输入信号的频率成比例。 第二电路是响应于输入信号具有第二逻辑电平而在接收输入电流的第二电容器两端的第二电压超过阈值电压时产生输出复位信号。 触发器是响应于输出控制信号而产生具有第一逻辑电平的信号输出,并且响应于输出复位信号复位并产生具有第二逻辑电平的信号输出。

    LDO REGULATOR WITH IMPROVED LOAD TRANSIENT PERFORMANCE FOR INTERNAL POWER SUPPLY

    公开(公告)号:US20160357206A1

    公开(公告)日:2016-12-08

    申请号:US15244289

    申请日:2016-08-23

    Inventor: Yong Feng Liu

    CPC classification number: G05F1/575 G05F1/565 G05F1/59 G05F3/30

    Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

    HIGH EFFICIENCY CLASS D AMPLIFIER WITH REDUCED GENERATION OF EMI
    54.
    发明申请
    HIGH EFFICIENCY CLASS D AMPLIFIER WITH REDUCED GENERATION OF EMI 有权
    具有降低EMI产生的高效级D放大器

    公开(公告)号:US20160329868A1

    公开(公告)日:2016-11-10

    申请号:US14715879

    申请日:2015-05-19

    Abstract: A class-D amplifier includes a signal processing block. The signal processing block generates a first processed signal representing a difference between a first differential signal and a second differential signal, when a duty cycle of the first differential signal is greater than that of the second differential signal. The signal processing block generates the first processed signal representing a reference DC level, when the duty cycle of the first differential signal is less than that of the second differential signal. A second processed signal representing a difference between the second differential signal and the first differential signal is generated when the duty cycle of the second differential signal is greater than that of the first differential signal, and the second processed signal representing the reference DC level is generated when the duty cycle of the second differential signal is less than that of the first differential signal.

    Abstract translation: D类放大器包括信号处理块。 当第一差分信号的占空比大于第二差分信号的占空比时,信号处理块产生表示第一差分信号和第二差分信号之间的差的第一处理信号。 当第一差分信号的占空比小于第二差分信号的占空比时,信号处理块产生表示参考DC电平的第一处理信号。 当第二差分信号的占空比大于第一差分信号的占空比时,产生表示第二差分信号和第一差分信号之间的差的第二处理信号,并且生成表示参考DC电平的第二处理信号 当第二差分信号的占空比小于第一差分信号的占空比时。

    LDO regulator with improved load transient performance for internal power supply
    58.
    发明授权
    LDO regulator with improved load transient performance for internal power supply 有权
    LDO稳压器,内部电源具有改善的负载瞬态性能

    公开(公告)号:US09454166B2

    公开(公告)日:2016-09-27

    申请号:US14543294

    申请日:2014-11-17

    Inventor: Yong Feng Liu

    CPC classification number: G05F1/575 G05F1/565 G05F1/59 G05F3/30

    Abstract: A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

    Abstract translation: 电压调节器包括反馈调节环路和驱动晶体管,其被配置为将电流输出到调节输出端。 瞬态恢复电路耦合到电压调节器电路,并且包括耦合到源极电流到驱动晶体管的控制端的第一晶体管,其中源电流除了响应于反馈调节环的操作而产生的电流之外。 第一晶体管响应于调节输出处的电压下降而选择性地致动。 瞬态恢复电路还包括耦合到从调节输出吸收电流的第二晶体管。 灌电流在调节器电路的静态工作模式下具有第一个非零幅值。 响应于调节输出处的电压增加,第二晶体管的操作被修改以将吸收电流增加到第二,更大,非零的幅度。

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