公开(公告)号：US09059207B2

公开(公告)日：2015-06-16

申请号：US13613747

申请日：2012-09-13

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Davood Shahrjerdi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/306 ,  H01L21/31144 ,  H01L21/324 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/78687

Abstract: A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel. The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

Abstract translation: 一种平面半导体器件，包括绝缘体上半导体（SOI）衬底，源极和漏极部分具有由多层应变通道分离的小于10nm的厚度。 SOI层的多层应变通道包括存在于SOI衬底的掩埋介电层上的第一晶格尺寸的第一层和与第一层直接接触的第二晶格尺寸的第二层 的多层应变通道部分。 功能栅极结构存在于SOI衬底的多层应变通道部分上。 具有多层通道的半导体器件也可以是finFET半导体器件。

公开(公告)号：US08946033B2

公开(公告)日：2015-02-03

申请号：US13561352

申请日：2012-07-30

Applicant: Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

Abstract: A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

Abstract translation: 翅片finFET和其制造方法。 鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面 并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

公开(公告)号：US08728897B2

公开(公告)日：2014-05-20

申请号：US13342797

申请日：2012-01-03

Applicant: Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC: H01L21/336

CPC classification number: H01L29/66242 ,  H01L21/76232 ,  H01L22/20 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7371

Abstract: A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer.

Abstract translation: 提供了通过应变补偿和制造方法提高驱动电流的功率SiGe异质结双色晶体管（HBT）。 一种方法包括在包括子集电极层，集电极层，基极缓冲层，基极层和发射极缓冲层的器件的层中以连续稳定的浓度添加碳。

公开(公告)号：US20140038369A1

公开(公告)日：2014-02-06

申请号：US13565838

申请日：2012-08-03

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/845 ,  H01L27/1211

Abstract: Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins.

Abstract translation: 各种实施例包括形成半导体结构的方法。 在一个实施例中，一种方法包括：提供包括衬底和覆盖衬底的一组鳍片的前体结构; 在翅片组中的翅片之间形成虚拟外延; 掩蔽该组散热片中的第一组散热片和在一组翅片中的第一组翅片之间的虚设外延; 去除所述虚拟外延以暴露第二组散热片; 在暴露的翅片之间形成第一原位掺杂外延; 掩蔽该组散热片中的第二组翅片和在该组翅片中的第二组翅片之间的原位掺杂的外延; 揭开第一组翅片; 去除第一组翅片之间的虚拟外延层以暴露第一组翅片; 以及在所述暴露的鳍之间形成第二原位掺杂的外延。

公开(公告)号：US08642415B2

公开(公告)日：2014-02-04

申请号：US13487511

申请日：2012-06-04

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

IPC: H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

Abstract translation: 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

公开(公告)号：US20140001561A1

公开(公告)日：2014-01-02

申请号：US13534522

申请日：2012-06-27

Applicant: Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

Abstract: A CMOS device structure and method of manufacturing the same are provided. The CMOS device structure includes a substrate having a first region and a second region. The CMOS device structure further includes a first gate formed in the first region overlying a first channel region in the substrate. The CMOS device structure further includes a first pair of source/drain regions formed in the first region on either side of the first channel region. Each region of the pair of source/drain regions has a substantially V-shaped concave top surface.

Abstract translation: 提供了一种CMOS器件结构及其制造方法。 CMOS器件结构包括具有第一区域和第二区域的衬底。 CMOS器件结构还包括形成在覆盖衬底中的第一沟道区域的第一区域中的第一栅极。 CMOS器件结构还包括形成在第一沟道区两侧的第一区域中的第一对源/漏区。 一对源极/漏极区域中的每个区域具有大致V形的凹顶表面。

公开(公告)号：US20130334571A1

公开(公告)日：2013-12-19

申请号：US13526840

申请日：2012-06-19

Applicant: Alexander Reznicek ,  Thomas N. Adam ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

Inventor： Alexander Reznicek ,  Thomas N. Adam ,  Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana

IPC: H01L29/78 ,  H01L29/24 ,  H01L21/20

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

Abstract: A smooth germanium layer which can be grown directly on a silicon semiconductor substrate by exposing the substrate to germanium precursor in the presence of phosphine at temperature of about 350C. The germanium layer formation can be achieved with or without a SiGe seed layer. The process to form the germanium layer can be integrated into standard CMOS processing to efficiently form a structure embodying a thin, highly strained germanium layer. Such structure can enable processing flexibility. The germanium layer can also provide unique physical properties such as in an opto-electronic devices, or to enable formation of a layer of group III-V material on a silicon substrate.

Abstract translation: 可以在约350℃的温度下，在磷化氢存在下将衬底暴露于锗前体，可直接在硅半导体衬底上生长的光滑的锗层。 可以在有或没有SiGe种子层的情况下实现锗层形成。 形成锗层的过程可以集成到标准CMOS处理中，以有效地形成体现薄的，高度应变的锗层的结构。 这种结构可以实现处理灵活性。 锗层还可以提供独特的物理性质，例如在光电子器件中，或者能够在硅衬底上形成III-V族材料层。

公开(公告)号：US20130307076A1

公开(公告)日：2013-11-21

申请号：US13472605

申请日：2012-05-16

Applicant: Kangguo Cheng ,  Thomas N. Adam ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Kangguo Cheng ,  Thomas N. Adam ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L27/0802 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.

Abstract translation: 公开了一种鳍式电阻器和制造方法。 散热片电阻器包括以具有外延区域的交替图案的线性图案布置的多个散热片。 退火将掺杂剂从外延区域扩散到鳍片中。 触头连接到端点外延区域，以允许电阻器连接到更复杂的集成电路。

公开(公告)号：US20130285123A1

公开(公告)日：2013-10-31

申请号：US13457980

申请日：2012-04-27

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/20

CPC classification number: H01L21/02609 ,  H01L21/265 ,  H01L21/28026 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.

Abstract translation: 具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。 嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。 去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。 各向异性蚀刻在凹槽的通道侧壁中产生刻面。 小面相遇时，形成顶点。 顶点的深度由第二蚀刻深度（阶梯深度）决定。 顶点的横向位置由第一间隔件的厚度决定。 在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。

公开(公告)号：US20130249006A1

公开(公告)日：2013-09-26

申请号：US13424787

申请日：2012-03-20

Applicant: Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Alexander Reznicek

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66628 ,  H01L29/7834

Abstract: A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.

Abstract translation: 在平面场效应晶体管的平面源极/漏极区域或与鳍状场效应晶体管的沟道区域相邻的半导体鳍片的一部分的表面上形成下部凸起的源极/漏极区域。 形成并平坦化至少一个接触层介电材料层，并且在该至少一个接触层电介质材料层中形成延伸到下凸起源/漏区的接触通孔。 上凸起的源/漏区形成在下凸起的源/漏区的顶表面上。 在接触通孔内形成金属半导体合金部分和接触通孔结构。 上部隆起源极/漏极区域的形成被限制在接触通孔的底部，从而通过未被接触的源极/漏极区域中的任何额外的凸起结构来防止寄生电容的形成和增加。