公开(公告)号：US09229803B2

公开(公告)日：2016-01-05

申请号：US13720536

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Vilas K. Sridharan ,  James M. O'Connor ,  Jaewoong Sim

IPC: G06F11/10 ,  G06F12/08

CPC classification number: G06F11/1064 ,  G06F12/0893

Abstract: A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.

Abstract translation: 管理存储器的方法包括在高速缓冲存储器中的第一位置安装第一高速缓存线并接收写入请求。 响应于写入请求，第一个缓存线根据写入请求进行修改并标记为脏。 还响应于写入请求，安装第二高速缓存线，该第二高速缓存线在高速缓冲存储器的第二位置处复制根据写入请求修改的第一高速缓存线。

公开(公告)号：US09183055B2

公开(公告)日：2015-11-10

申请号：US13761985

申请日：2013-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Bradford M. Beckmann ,  Mithuna S. Thottethodi ,  James M. O'Connor ,  Mauricio Breternitz ,  Lisa R. Hsu ,  Gabriel H. Loh ,  Yasuko Eckert

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5016 ,  G06F9/5011 ,  G06F12/0875 ,  G06F2212/45

Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.

Abstract translation: 所描述的实施例包括从用于执行操作的计算设备中的一组资源中选择资源的选择机制。 在一些实施例中，选择机制被配置为在从一组表中选择的表中执行查找，以从资源集合中识别资源。 当所识别的资源不可用于执行操作并且直到选择资源来执行操作时，选择机制被配置为识别表中的下一个资源，并且当下一个资源可用时选择用于执行操作的下一个资源 用于执行操作。

公开(公告)号：US09087561B2

公开(公告)日：2015-07-21

申请号：US13724669

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthew R. Poremba ,  Gabriel H. Loh

IPC: G06F12/04 ,  G11C7/10 ,  G06F12/08

CPC classification number: G11C7/1072 ,  G06F12/0886 ,  G06F2212/1041 ,  G06F2212/601

Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.

Abstract translation: 提供数据缓存方法和系统。 提供了一种用于混合高速缓存系统的方法，其将具有第一标签字段和第一数据字段的未分割模式之间的高速缓存行的一个或多个高速缓存行的模式动态地改变为具有第二标签字段的分割模式，第二标记字段 数据字段小于第一数据字段和映射页面字段，以提高在处理器中正在执行的工作流的高速缓存访​​问效率。 提供了混合高速缓存系统，其中高速缓存被配置为以未分割模式或分离模式操作一个或多个高速缓存行。 该系统被配置为将缓存行的模式从未分割模式动态地改变到分割模式，以提高由处理器执行的工作流的高速缓存访​​问效率。

公开(公告)号：US20150199150A1

公开(公告)日：2015-07-16

申请号：US14156071

申请日：2014-01-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Hye Ran Jeon ,  Gabriel H. Loh

IPC: G06F3/06

CPC classification number: G11C7/1006 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G11C7/1078 ,  G11C11/4093

Abstract: The described embodiments include a memory with a memory array and logic circuits. In these embodiments, logical operations are performed on data from the memory array by reading the data from the memory array, performing a logical operation on the data in the logic circuits, and writing the data back to the memory array. In these embodiments, the logic circuit is located in the memory so that the data read from the memory array need not be sent to another circuit (e.g., a processor coupled to the memory, etc.) to have the logical operation performed.

Abstract translation: 所描述的实施例包括具有存储器阵列和逻辑电路的存储器。 在这些实施例中，通过从存储器阵列读取数据，对逻辑电路中的数据执行逻辑运算，并将数据写回存储器阵列，对来自存储器阵列的数据执行逻辑运算。 在这些实施例中，逻辑电路位于存储器中，使得从存储器阵列读取的数据不需要发送到另一个电路（例如，耦合到存储器的处理器等）以执行逻辑操作。

公开(公告)号：US20150155876A1

公开(公告)日：2015-06-04

申请号：US14551147

申请日：2014-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20140380003A1

公开(公告)日：2014-12-25

申请号：US13926765

申请日：2013-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Lisa R. Hsu ,  Gabriel H. Loh ,  James Michael O'Connor ,  Nuwan S. Jayasena

IPC: G06F9/48 ,  G06F3/06

CPC classification number: G06F3/067 ,  G06F9/4881 ,  G06F9/5033 ,  G06F12/1036 ,  G06F2212/302

Abstract: Methods, systems and computer readable storage mediums for more efficient and flexible scheduling of tasks on an asymmetric processing system having at least one host processor and one or more slave processors, are disclosed. An example embodiment includes, determining a data access requirement of a task, comparing the data access requirement to respective local memories of the one or more slave processors selecting a slave processor from the one or more slave processors based upon the comparing, and running the task on the selected slave processor.

Abstract translation: 公开了用于在具有至少一个主处理器和一个或多个从属处理器的非对称处理系统上更有效和灵活地调度任务的方法，系统和计算机可读存储介质。 一个示例实施例包括：确定任务的数据访问需求，将数据访问要求与一个或多个从属处理器的相应本地存储器进行比较，所述一个或多个从属处理器基于比较而从一个或多个从属处理器中选择从属处理器，并且执行任务 在所选的从属处理器上。

公开(公告)号：US20140372711A1

公开(公告)日：2014-12-18

申请号：US13917033

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Niladrish Chatterjee ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/161 ,  G06F13/1694

Abstract: A memory accessing agent includes a memory access generating circuit and a memory controller. The memory access generating circuit is adapted to generate multiple memory accesses in a first ordered arrangement. The memory controller is coupled to the memory access generating circuit and has an output port, for providing the multiple memory accesses to the output port in a second ordered arrangement based on the memory accesses and characteristics of an external memory. The memory controller determines the second ordered arrangement by calculating an efficient row burst value and interrupting multiple row-hit requests to schedule a row-miss request based on the efficient row burst value.

Abstract translation: 存储器访问代理包括存储器访问生成电路和存储器控制器。 存储器访问生成电路适于以第一有序布置生成多个存储器访问。 存储器控制器耦合到存储器存取产生电路，并且具有输出端口，用于基于存储器访问和外部存储器的特性以第二有序布置提供对输出端口的多个存储器访问。 存储器控制器通过计算有效的行脉冲串值和中断多个行命中请求来基于有效的行脉冲串值来调度行错请求来确定第二排序。

公开(公告)号：US20140181414A1

公开(公告)日：2014-06-26

申请号：US14055869

申请日：2013-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yasuko Eckert ,  Gabriel H. Loh ,  Mauricio Breternitz ,  James M. O'Connor ,  Srilatha Manne ,  Nuwan S. Jayasena ,  Mithuna S. Thottethodi

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F1/3225 ,  G06F1/3275 ,  G06F12/0848 ,  G06F12/0888 ,  G06F12/0897 ,  Y02D10/13 ,  Y02D10/14

Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.

Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，其中第一存储体断电。 作为响应，向第二组写入请求，指示存储在掉电第一存储体中的数据，高速缓存控制器确定数据的相应旁路条件。 如果旁路条件超过阈值，则高速缓存控制器使存储在第二组中的数据的任何副本无效。 如果旁路条件不超过阈值，则高速缓存控制器将具有干净状态的数据存储在第二存储体中。 高速缓存控制器将这些数据写入较低级别的内存。

公开(公告)号：US20140176187A1

公开(公告)日：2014-06-26

申请号：US13726145

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20140143502A1

公开(公告)日：2014-05-22

申请号：US13736254

申请日：2013-01-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Jaewoong Sim

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0888

Abstract: The described embodiments include a cache controller with a prediction mechanism in a cache. In the described embodiments, the prediction mechanism is configured to perform a lookup in each table in a hierarchy of lookup tables in parallel to determine if a memory request is predicted to be a hit in the cache, each table in the hierarchy comprising predictions whether memory requests to corresponding regions of a main memory will hit the cache, the corresponding regions of the main memory being smaller for tables lower in the hierarchy.

Abstract translation: 所描述的实施例包括在高速缓存中具有预测机制的高速缓存控制器。 在所描述的实施例中，预测机制被配置为并行地在查找表的层次中的每个表中执行查找，以确定存储器请求是否被预测为高速缓存中的命中，层级中的每个表包括是否存储 对主存储器的对应区域的请求将到达高速缓存，主存储器的对应区域对于层级中较低的表来说较小。